Principal Digital Design Engineer

onsemi • Allen, TX

2d

About The Position

The Principal Digital Design Engineer will own the IO subsystem for onsemi’s microcontroller platform, based in Allen, Texas. The role defines, architects, and delivers a highly configurable IO subsystem that supports product requirements across multiple end markets. The subsystem is intended to be flexible and reusable while optimized for performance, power, and area.

As the technical leader for the IO subsystem, the Principal Engineer drives architecture, RTL implementation, and design automation strategy. The role works closely with system architecture, product lines, DFT, physical design, verification, and software teams, and contributes technical execution and cross-functional leadership to influence platform direction.

Requirements

• Bachelor’s degree in Electrical Engineering or a related field.
• 10+ years of experience in digital IC design with a strong RTL development background.
• Expert-level proficiency in SystemVerilog RTL design.
• Strong experience with Python for design automation and tool development.
• Solid experience with UVM-based verification methodologies and testbench development.
• Strong understanding of UPF, synthesis, STA, and timing signoff flows.
• Experience working with DFT concepts and integration.
• Strong cross-functional collaboration skills across design, verification, physical design, and product teams.

Nice To Haves

• Master’s degree preferred.

Responsibilities

• Own the architecture and development of the IO subsystem, ensuring configurability and reuse across multiple products.
• Define subsystem-level specifications, interfaces, and integration strategy aligned with platform and product requirements.
• Define and implement parameterized and Python generator-based design approaches for scalable, configurable subsystem instantiation.
• Drive creation of automatically generated testbenches and verification environments using UVM frameworks and AI-assisted techniques.
• Develop high-quality SystemVerilog RTL compatible with automated generation flows and maintainable at scale.
• Support synthesis, STA, and timing closure activities to deliver signoff-ready designs.
• Collaborate with verification, DFT, and physical design teams to achieve first-time-right silicon.
• Apply AI/ML techniques to improve design productivity, including code-generation assistance, verification acceleration, and design-space exploration.
• Drive PPA optimization while maintaining configurability and reuse targets.
• Establish best practices for design automation, code generation, and methodology standardization across the organization.

What This Job Offers

• Job Type: Full-time
• Career Level: Principal