Principal Digital Design Engineer

NAVITAS SEMICONDUCTOR USA, INC. • Torrance, CA

6d • $170,000 - $190,000 • Onsite

About The Position

Navitas Semiconductor is seeking a Principal Digital Design Engineer to contribute to digital design and verification for ASICs and power management integrated circuits. The role spans digital architecture and RTL design through verification, tape-out, and post-silicon validation, including integration with analog and mixed-signal blocks. The engineer will use standard ASIC flows and Cadence tools, develop SystemVerilog/UVM testbenches, drive coverage closure, and apply formal and mixed-signal verification where appropriate.

After fabrication, the role includes developing FPGA-based test builds with Xilinx tools to validate and characterize PMIC silicon, leading silicon debug and root-cause analysis, and incorporating findings into future design and verification. The engineer will also improve automation and team flows, lead reviews, provide technical direction and mentorship, and collaborate with analog, layout, validation, and test teams. The position is based in Torrance, California, and is full time.

Requirements

• Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field.
• At least 5 years of industry experience in digital hardware design (ASIC, FPGA, or embedded hardware).
• Significant experience with SystemVerilog for design and verification.
• Solid understanding of ASIC design flows, including RTL design, synthesis, timing closure, and verification.
• Experience with digital simulation tools such as Xcelium, Questa, or Vivado Simulator.
• Experience with Xilinx FPGA development tools (Vivado or ISE) for prototyping and silicon validation.
• Proficiency in scripting for automation and test, such as Python, Tcl, or Bash.
• Strong digital design fundamentals and hardware debugging skills.
• Proficiency with version control software such as Git.
• Familiarity and experience with simulation and verification features and methods, including assertions, linting, threading, and metric-driven verification such as code, conditional branch, toggle, FSM branch, and functional coverage.
• Knowledge of synchronous and asynchronous design, FSMs, clock-domain crossing, reset strategies, and low-power techniques.
• Knowledge of ASIC flows including RTL, synthesis, static timing analysis, DFT, equivalence checking, place-and-route handoff, and signoff.
• Knowledge of verification methodology, including SVA, functional and code coverage, constrained-random testing, and formal verification concepts.
• Knowledge of PMIC and power-electronics fundamentals, including DC-DC converter control, sequencing, protection and fault handling, trimming, and digital interaction with analog blocks.
• Knowledge of mixed-signal modeling and co-simulation concepts.
• Knowledge of serial protocols including I²C, SPI, and PMBus/SMBus.
• Knowledge of standard cell libraries, SDC timing constraints, and process-corner and variation effects.
• Knowledge of post-silicon validation and ATE test concepts.
• Hands-on experience with Cadence tools such as Xcelium, Genus, Conformal, Modus, Tempus/Innovus, and Voltus.
• Experience using Xilinx Vivado and FPGA prototyping for silicon validation.
• Lab skills using oscilloscopes, logic analyzers, protocol analyzers, and bench equipment for silicon debug.
• Ability to translate product-level requirements into digital architecture and root-cause complex failures across pre-silicon, FPGA, and silicon environments.
• Ability to balance area, power, timing, schedule, and risk; communicate technical issues across disciplines; and manage multiple projects or blocks under tape-out deadlines.
• Independence, ownership, and accountability for design contributions, with attention to detail and a pragmatic, schedule-aware approach.
• Comfort working in a smaller team where individual contributions have significant impact.

Nice To Haves

• Master's or Ph.D. in Electrical Engineering, Computer Engineering, or a related field.
• At least 8 years of industry experience in digital hardware design (ASIC, FPGA, or embedded hardware).
• Experience designing digital circuits for PMICs, DC-DC converters, battery management, or other power-management products.
• Hands-on experience with standard-cell logical synthesis and writing or refining SDC constraints.
• Experience with place and route, including floor planning, placement, clock-tree synthesis, routing, and timing closure.
• Experience with static timing analysis and signoff across corners and modes, including timing ECOs.
• Experience with power-integrity analysis.
• Experience with logical equivalence checking across RTL, synthesized, and post-layout netlists.
• Familiarity with physical verification (DRC/LVS) and working with layout teams to resolve issues.
• Experience with DFT insertion and ATPG, and supporting ATE test bring-up.
• Experience with CDC analysis and lint signoff tools.
• Multiple successful tape-outs, ideally on mature mixed-signal or BCD processes used in power management.
• Familiarity with embedding third-party IP, such as MCUs and memories, within a network of digital accelerators.

Responsibilities

• Design and implement ASIC digital blocks using Verilog/SystemVerilog and standard ASIC design flows.
• Participate in pre-silicon simulation and verification using Cadence tools and standard cell libraries.
• Develop and maintain UVM/SystemVerilog testbenches, including functional coverage, SVA assertions, and constrained-random stimulus.
• Analyze code and functional coverage, identify gaps, and drive coverage closure and improvements to verification suites.
• Apply formal verification to property checking, connectivity, register, and FSM verification where appropriate.
• Build mixed-signal verification using real-number modeling or AMS co-simulation.
• Support ASIC tape-out activities, including synthesis, static timing analysis, and design signoff.
• Develop FPGA-based test builds using Xilinx tools to validate and characterize fabricated PMIC silicon.
• Interface and integrate digital control logic with analog and mixed-signal power-management blocks.
• Own digital architecture specifications from product requirements through tape-out.
• Lead design and verification reviews and follow team coding, verification, and methodology standards.
• Mentor junior engineers and provide technical direction across projects.
• Lead post-silicon debug and root-cause analysis, and feed silicon learnings back into design and verification.
• Evaluate and improve design and verification flows and tools to increase productivity and reuse.
• Write and maintain automation scripts for regression testing, build flows, and hardware validation.
• Collaborate with analog designers, layout, validation, and test engineers on robust and reliable PMIC designs.

Benefits

• Comprehensive health, dental, and vision coverage.
• Unlimited PTO.
• Competitive compensation package including base salary, bonus, and equity awards.
• Access to leadership, cross-functional collaboration, and resources to support innovation and execution.

What This Job Offers

• Job Type: Full-time
• Career Level: Principal