Senior SoC Design Engineer

Microsoft•Redmond, WA
•$119,800 - $261,000

About The Position

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) supports Microsoft’s cloud infrastructure and Intelligent Cloud mission. The Senior SoC Design Engineer will work on the Microsoft Artificial Intelligence System on Chip (AISoC) Silicon team in a fast-moving technical environment. The role contributes to high-performance, high-bandwidth SoC designs, from IP microarchitecture specifications and RTL design through SoC integration, synthesis, and static design checks. The engineer works with architecture, verification, and physical design teams to ensure designs are implemented and verified according to specification.

Requirements

  • Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or a related field and at least 1 year of technical engineering experience; or a master's degree in one of these fields and at least 4 years of experience; or a bachelor's degree in one of these fields and at least 5 years of experience; or equivalent experience.
  • Ability to meet Microsoft, customer, and/or government security screening requirements, including passing the Microsoft Cloud Background Check upon hire or transfer and every two years thereafter.
  • Must provide proof of citizenship, U.S. residency, or other protected status to assess eligibility for access to export-controlled information; citizenship is verified with a valid passport, with other documents accepted for lawful permanent residents, refugees, and asylees where applicable.

Nice To Haves

  • At least 8 years of digital design expertise, including microarchitecture specification development, Verilog/SystemVerilog RTL coding, and CDC/lint closure.
  • At least 6 years of experience delivering successful IP, ASIC, or SoC designs.
  • At least 4 years of experience in synthesis, timing constraints, PPA trade-offs, and post-silicon debug.
  • At least 4 years of experience designing fabric/Network-on-Chip or networking ASICs, or complex control logic.

Responsibilities

  • Develop IP microarchitecture specifications.
  • Design Register Transfer Level (RTL).
  • Integrate systems on chip, including clocking and resets.
  • Perform synthesis and static checks, including lint and clock/reset domain crossing checks.
  • Work with architecture, verification, and physical design teams to ensure designs are implemented and verified to specification.
© 2026 Teal Labs, Inc
Privacy PolicyTerms of Service