SoC Logic Design Engineer

Intel Corporation•Santa Clara, CA

1d•$105,650 - $149,150•Onsite

About The Position

As a SoC Logic Design Engineer, you will contribute to the development, coding, and simulation of system-on-chip (SoC) designs. You will integrate logic from IP blocks and subsystems into complete chip designs and help ensure power, performance, area, and timing goals are met. The role is part of Intel's Data Center Group (DCG), which delivers solutions for data-centric computing. You will collaborate on projects that shape the performance, security, and efficiency of Intel's data center offerings.

Requirements

Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field, with 0–1 years of hands-on logic design experience through internships, academic projects, coursework, or hands-on training; or a Master's degree in one of these fields with no prior professional experience.
Advanced experience with RTL coding languages such as Verilog or VHDL.
Basic knowledge of industry-standard tools for logic design, synthesis, and simulation, such as Synopsys Design Compiler or Cadence Xcelium.
Basic knowledge of power, performance, and area optimization in SoC designs.
Basic knowledge of timing analysis and static timing tools.

Nice To Haves

Strong analytical and problem-solving skills with attention to detail.
Effective communication skills for collaborating with cross-functional teams.
Experience on academic or industry projects involving SoC design and IP integration.
Interest in learning and contributing to advancements in semiconductor technology.

Responsibilities

Design and implement logic for SoC blocks and subsystems using register transfer level (RTL) coding techniques.
Integrate IP blocks and subsystems into full-chip SoC designs, ensuring seamless functionality.
Conduct quality checks across logic design, including RTL coding, timing, power, and area convergence.
Optimize logic designs to meet power, performance, area, and timing targets.
Review verification plans and resolve failing RTL tests to ensure design features are correct.
Collaborate with IP providers to integrate and validate IPs for SoC-level designs.
Follow secure development practices to meet security objectives and address security threats in designs.
Drive compliance with quality assurance standards for successful IP and SoC handoff.