Logic Design Engineer
About The Position
Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) develops and operates the infrastructure and foundational technologies that support Microsoft's online businesses and Azure platform. Its Compute Silicon & Manufacturing Engineering organization designs, develops, manufactures, and packages computer chips, including Azure Cobalt. The Logic Design Engineer will join the Fabric IP Design team, which supports the planning, quality, delivery, scale, and sustainability of Microsoft cloud hardware manufacturing. The role contributes to the design of advanced memory-subsystem components and complex coherent fabrics and bridge IPs. It covers the design flow from RTL coding through lint, CDC, and timing closure, and involves collaboration with verification, performance modeling, physical design, design-for-test, and other teams. The engineer will also develop automation and AI-based solutions to improve organizational efficiency.
Requirements
- At least 5 years of related technical engineering experience; alternatively, a bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field plus at least 5 years of technical engineering or internship experience; a master's degree in one of those fields plus at least 3 years of technical engineering or internship experience; or a doctorate in one of those fields.
- At least 3 years of digital logic design experience for ASIC or FPGA.
Nice To Haves
- Knowledge of front-end tools, including Verilog simulators, connectivity tools, CDC checkers, low-power static checkers, and linting tools.
- Proficiency in computer architecture, digital design, and CPU/SoC design principles through CPU, SoC, or IP development.
- Experience and knowledge of design clock crossings and power/UPF.
- Ability to write scripts using Perl, Tcl, Python, or similar languages.
- Experience using generative AI technologies and developing agents or skills.
- Experience building and integrating IP such as protocol bridges, PCIe, cache controllers, memory controllers and DDR, or security engines.
- Experience building functional fabrics using coherent and non-coherent protocols.
- Familiarity with industry-standard interface protocols such as AXI or CHI.
- Familiarity with synthesis and STA tools.
- Good verbal and written communication skills.
Responsibilities
- Contribute to a design team developing advanced components of the memory subsystem.
- Develop automation and AI-based solutions to improve organizational efficiency.
- Own design blocks within complex, coherent fabrics and bridge IPs.
- Manage design-flow activities, including RTL coding, lint, CDC, and timing closure.
- Collaborate with team members to define interfaces and make optimal design choices.
- Work with verification teams to develop test plans and ensure functional correctness.
- Coordinate with performance modeling, physical design, design-for-test, and other teams to optimize tradeoffs.
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What This Job Offers
Job Type
Full-time
Career Level
Mid Level
Education Level
No Education Listed
