SoC Physical Design Engineer

Meta•Redmond, WA

2d•$178,000 - $250,000

About The Position

Meta’s Reality Labs Silicon team develops custom silicon for advanced AI-enabled wearables. The SoC Physical Design Engineer collaborates with SoC architects, front-end and back-end hardware designers, and power/performance teams to physically implement IP, subsystems, and chip top-level designs in advanced technology nodes. The role develops methodologies across the physical design cycle—including floorplanning, physical synthesis, placement, clock-tree synthesis, routing, and static timing analysis—to optimize power, performance, and area and ensure design convergence. The position brings cutting-edge technologies into high-volume consumer products.

Requirements

Bachelor's degree in Computer Science, Computer Engineering, Electrical Engineering, a relevant technical field, or equivalent practical experience.
8+ years of experience in SoC or ASIC physical design.
Hands-on RTL-to-GDSII experience at 3nm or below, including floorplanning, physical synthesis, placement, clock-tree synthesis, routing, static timing analysis, and signoff.
Experience with low-power implementation techniques, including power gating, voltage areas or islands, UPF, and DVFS.
Experience with static timing analysis, including defining timing constraints, exceptions, and PVT corners and modes for functional and DFT signoff, and accounting for OCV/POCV and crosstalk effects.
Experience with EDA tools such as Fusion Compiler/Genus, ICC2/Innovus, PrimeTime/Tempus, RedHawk/Voltus, or equivalent.
Proficiency in TCL, Python, or Perl scripting and ability to read Verilog netlists and RTL.
Experience collaborating across RTL, DV, DFx, package, and vendor teams.

Nice To Haves

Ownership of block-level or full-chip power-grid planning, including dedicated macro supplies, power-switch chaining, MiM/decoupling capacitors, and EM/IR closure.
Track record of defining signoff criteria and leading tapeout execution.
Tapeout experience at 3nm or below.
Experience adhering to and implementing responsible, ethical AI practices, such as risk assessment, bias mitigation, and quality and accuracy reviews.
Experience applying ML-driven implementation tools such as DSO.ai or Cerebrus, or LLM agents, to flow debugging or quality-of-results improvement with measurable impact.
Ongoing AI skill development, such as prompt/context engineering or agent orchestration, and awareness of emerging AI technologies.
Background in physically aware synthesis of ultra-low-power designs, including custom recipes and application options, low-voltage PPA exploration, and UPF authoring.
Experience managing die-area budgets, including full-chip partitioning, beachfront allocations, channel planning, and pipeline/feedthrough insertion.
Facility with advanced clock-tree synthesis, such as multi-source or H-tree approaches at block or chip level, including clock-power reduction and hierarchical techniques.
Experience leading chip-level timing closure across multi-corner/multi-mode scenarios, authoring I/O timing constraints, parsing flat timing reports, and implementing timing ECOs.
Experience with 3D-IC structures such as TSVs, EDA tools, and signoff methodologies.
Master’s or PhD degree in Electrical Engineering, Computer Engineering, or an equivalent area.

Responsibilities

Lead physical implementation from floorplanning through tapeout, including physically aware ultra-low-power logic synthesis, place-and-route, static timing analysis, and EM/IR across all levels of the SoC hierarchy.
Define physical design methodologies and flows that realize power and timing intent and meet wearable-device power and thermal requirements.
Identify and resolve congestion, timing, and power bottlenecks, and develop automation and AI-assisted flows to improve throughput and quality of results.
Collaborate with RTL designers to provide implementation feedback that shapes microarchitecture for power- and area-efficient timing closure.
Work with package engineers to ensure the floorplan, clock tree, and power plan meet product-level power delivery, signal integrity, thermal, and routability requirements.
Partner with design verification and DFx teams to ensure physical implementation supports gate-level functional correctness, debug, and testability requirements.
Drive EDA vendor engagement, tool evaluations, and flow improvements.