HBM SoC Physical Design Engineer

Micron • Richardson, TX

6d

About The Position

As a SoC Physical Design Engineer in Micron Technology’s Heterogeneous Integration Group, you will implement advanced HBM SoC logic/base-die designs from netlist to GDSII. You will collaborate with RTL design, verification, DFT, IP providers, packaging and assembly, and manufacturing teams to achieve performance, power, and area targets and deliver robust signoff collateral for tape-out. This hands-on position offers opportunities to own blocks or top-level integration across multiple product generations.

Requirements

• Strong experience implementing SoC physical design from netlist to GDSII on advanced nodes and complex designs.
• Proficiency with industry EDA tools such as Cadence Innovus/Tempus, Synopsys ICC2/PrimeTime, Siemens Calibre, or equivalent.
• Solid understanding of STA fundamentals, clocking, SDC constraints, and closure techniques such as buffering, path shaping, and useful skew.
• Experience with power intent and power-delivery considerations, including UPF/CPF concepts, power-grid planning, and power-gating implications.
• Familiarity with physical verification and signoff concepts, including DRC, LVS, ERC, parasitic-extraction awareness, and signoff handoff quality.
• Minimum 10 years of experience in a related field.
• Proven ability to mentor and develop engineers early in their careers.

Nice To Haves

• Experience with HBM/DRAM-adjacent SoC designs or memory-subsystem-heavy SoCs.
• Bachelor’s or master’s degree in electrical engineering, computer engineering, or a related field.

Responsibilities

• Own physical implementation for SoC blocks and/or top-level designs, including floor-planning, placement, clock-tree synthesis, routing, and physical optimization to meet PPA targets.
• Drive setup and hold timing closure across multi-mode/multi-corner scenarios in partnership with RTL, architecture, and STA/signoff teams.
• Integrate and implement complex IP, such as controllers, microcontrollers, NOC, interfaces, MBIST/DFT logic, buffers, and PHY-adjacent logic, with attention to physical integration, timing, and power integrity.
• Perform or coordinate physical signoff, including DRC/LVS, IR drop/EM, and timing signoff, and resolve violations efficiently.
• Partner with DFT teams to ensure scan and MBIST requirements are physically realizable without compromising PPA or schedule.
• Work with packaging, assembly, test, probe, and manufacturing collaborators to ensure builds meet manufacturability and quality requirements.
• Support tape-out execution, including checklists, ECO flows, and signoff reviews.
• Contribute to post-silicon debug by correlating silicon behavior with physical design, STA, and power analysis.
• Identify flow gaps and improve productivity through scripting, automation, and best-practice methodology development.

Benefits

• Choice of medical, dental, and vision plans.
• Programs to help protect income in the event of illness or injury.
• Paid family leave.
• Paid time off.
• Paid holidays.

What This Job Offers

• Job Type: Full-time
• Career Level: Senior
• Education Level: No Education Listed