SoC Logic Design Engineer

Intel•Santa Clara, CA

22h•Onsite

About The Position

As a SoC Logic Design Engineer in Intel's Data Center Group (DCG), you will contribute to the development, coding, and simulation of system-on-chip (SoC) designs. You will integrate logic from IP blocks and subsystems into complete chip designs, helping ensure power, performance, area, and timing goals are met. The work contributes to Intel data center solutions and the performance, security, and efficiency of its data center offerings. The role involves designing and implementing logic for SoC blocks and subsystems using register transfer level (RTL) techniques; integrating and validating IP and subsystems; checking and optimizing design quality, timing, power, and area; reviewing verification plans and resolving failing RTL tests; following secure development practices; and supporting quality assurance and successful IP and SoC handoff. This is an on-site position, with primary locations in Santa Clara, California, and additional locations in Folsom, California, and Hillsboro, Oregon.

Requirements

Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field, with 0–1 years of hands-on logic design experience gained through internships, academic projects, coursework, or hands-on training; alternatively, a master's degree in Electrical Engineering, Computer Engineering, or a related field with no prior professional experience.
Advanced experience with RTL coding languages such as Verilog or VHDL.
Basic knowledge of industry-standard logic design, synthesis, and simulation tools, such as Synopsys Design Compiler and Cadence Xcelium.
Basic knowledge of power, performance, and area optimization in SoC designs.
Basic knowledge of timing analysis and static timing tools.

Nice To Haves

Strong analytical and problem-solving skills with attention to detail.
Effective communication skills for collaboration with cross-functional teams.
Experience with academic or industry projects involving SoC design and IP integration.
Interest in learning and contributing to advances in semiconductor technology.

Responsibilities

Design and implement logic for SoC blocks and subsystems using RTL coding techniques.
Integrate IP blocks and subsystems into full-chip SoC designs and ensure seamless functionality.
Conduct quality checks across RTL coding, timing, power, and area convergence.
Optimize logic designs to meet power, performance, area, and timing targets.
Review verification plans and resolve failing RTL tests to ensure design features are correct.
Collaborate with IP providers to integrate and validate IPs for SoC-level designs.
Follow secure development practices to meet security objectives and address design security threats.
Drive compliance with quality assurance standards for successful IP and SoC handoff.