Senior mixed-signal electrical engineer (Board Level)

ASML•San Jose, CA

43d•$119,600 - $164,450

About The Position

This role involves leading the design, analysis, and implementation of high-performance analog and mixed-signal circuits on board level. The engineer will be responsible for high-speed (>50 MSPS), high-precision (≥16-bit) DAC/ADC signal chains and low-noise, high-linearity, high dynamic range analog front-end (AFE) designs. A key aspect of the role is designing and developing precision high-voltage circuits with high frequency (>5 MHz), low distortion, and ultra-low offset (<1 mV), capable of operating in high-voltage environments up to ±225V with robust stability and reliability. The engineer will architect and optimize complete end-to-end signal chains, including DAC/ADC interfaces, amplification, filtering, driver stages, feedback loops, and calibration. Responsibilities also include performing modeling, simulation, and performance validation using both system-level (behavioral) and circuit-level (SPICE) models, and analyzing key performance parameters. Laboratory debugging, validation, and system bring-up using advanced equipment are crucial, as is identifying and resolving issues related to signal integrity, EMI/EMC, thermal effects, and parasitics. Collaboration with digital, FPGA, system, power, and software teams is essential for defining interfaces and supporting system integration. The role supports the full product lifecycle, from concept to volume production, including design validation, engineering validation, manufacturing support, and root cause analysis for field and production issues. Driving the adoption of advanced technologies and producing high-quality documentation are also key. Finally, the Senior Engineer will provide technical leadership and mentorship to junior engineers.

Requirements

Master’s or PhD degree in Electrical Engineering or a related field
Minimum 5+ years of experience in analog or mixed-signal circuit design (PhD graduates may qualify with less experience)
Strong background in analog circuit fundamentals, with experience in operational amplifiers and precision analog design, ADC/ADC interfacing and signal chain optimization, and high-speed and/or high-voltage analog systems.
Proficiency in circuit simulation tools: LTspice, TINA, Cadence, ADS, or equivalent
Programming skills for modeling and data analysis: Python, MATLAB, or similar
Hands-on lab experience with measurement and debug tools: Oscilloscopes, function generators, spectrum analyzers, network analyzers
Deep understanding of non-ideal analog effects: Noise, distortion, offset, drift, parasitic
Knowledge of signal integrity (SI) and power integrity (PI) principles
Strong system-level thinking, able to optimize across full signal chains
Ability to balance physical limitations with system performance requirements
Strong root cause analysis and debugging capabilities
Ability to solve complex, cross-domain engineering problems
Effective decision-making under uncertainty
Results-driven with strong ownership and accountability
Capable of working effectively in high-pressure, dynamic environments
Able to work both independently and collaboratively
Clear, concise, and professional technical communication
Ability to present complex technical concepts to both engineers and management
Familiarity with full product development lifecycle (design → validation → production)
Ability to work within structured processes and meet project timelines
Proficient in Microsoft Office Suite (Word, Excel, PowerPoint)
Capable of producing high-quality technical documentation and presentations

Nice To Haves

Experience in one or more of the following areas is highly desirable: Low-noise design (nV/√Hz level), High-linearity systems (>16-bit ENOB), Precision measurement systems, High-frequency analog design (MHz range and beyond)
Experience in high-end equipment or precision systems, such as semiconductor equipment (e.g., SEM, lithography, metrology systems), precision control systems (e.g., scan control, motion control), high-speed data acquisition systems
EDA tools, Xpedition preferred
Familiarity with high-speed interfaces (e.g., JESD204B-based ADC systems)
Experience working in global, cross-site teams
Prior experience in technical leadership or leading complex subsystem development

Responsibilities

Lead the design, analysis, and implementation of high-performance analog and mixed-signal circuits on board level, including high-speed (>50 MSPS), high-precision (≥16-bit) DAC/ADC signal chains and low-noise, high-linearity, high dynamic range analog front-end (AFE) designs.
Design and develop precision high-voltage circuits with high frequency (>5 MHz), low distortion, and ultra-low offset (<1 mV), operating in high-voltage environments up to ±225V, with robust stability and reliability.
Architect and optimize complete end-to-end signal chains, including DAC/ADC interfaces, amplification, filtering, driver stages, feedback loops, and calibration.
Perform modeling, simulation, and performance validation, developing both system-level (behavioral) and circuit-level (SPICE) models, and analyzing key performance parameters such as noise, distortion, offset, drift, bandwidth, and stability.
Drive laboratory debugging, validation, and system bring-up, utilizing advanced lab equipment and identifying and resolving issues related to signal integrity, EMI/EMC, thermal effects, and parasitic.
Collaborate cross-functionally with digital, FPGA, system, power, and software teams to define hardware/firmware/software interfaces and support system-level integration and validation.
Support full product lifecycle, from concept to volume production, including design validation (DV), engineering validation (EVT), and manufacturing support, as well as root cause analysis (RCA) for field and production issues.
Drive adoption of advanced technologies and architectures in high-performance systems.
Produce high-quality documentation, including design specifications, simulation reports, and test reports.
Provide technical leadership and mentorship to junior engineers.