DE or Senior Director, Central Engineering - SoC Design & Modeling Methodologies

Renesas Electronics•San Jose, CA
•$275,500 - $344,500

About The Position

The Senior Director will lead workload and performance analysis, hardware/software optimization and co-design—including AI workloads—and SoC architecture. The role covers workload characterization, solution integration, performance/power tradeoffs, advanced SoC architecture, modeling methodologies, and design enablement strategies across multiple product lines. The position partners with product groups, platform teams, and executive leadership to define and analyze products and SoCs, and to advance design methodologies that accelerate innovation and enable reuse across the organization.

Requirements

  • MS or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related technical discipline.
  • 15 or more years of experience in semiconductor or SoC development.
  • 8 or more years of technical leadership experience.
  • Proven experience leading performance and workload analysis and hardware/software co-optimization.
  • Strong understanding of performance analysis, workload analysis, AI workloads, SoC architecture and integration, digital design methodologies, IP and subsystem development, hardware/software co-design, and SoC verification methodologies.
  • Hands-on experience with performance and workload benchmarking, virtual platforms and executable specifications, SoC performance modeling, and design and verification automation flows.

Nice To Haves

  • PhD in a relevant technical discipline.
  • Experience in platform design and translating customer-facing requirements into system-level requirements.

Responsibilities

  • Define and drive the strategic roadmap for workload analysis and performance for IPs and products across the company.
  • Lead architecture performance reviews and set technical direction for complex IP, SoC, and subsystem developments.
  • Establish best practices for hardware/software co-design and model-based development.
  • Provide technical leadership for cross-functional teams spanning architecture, design, verification, emulation, and software.
  • Define and analyze AI workloads and the performance needed for those workloads.
  • Build and lead high-performing engineering teams.
  • Mentor directors, principal engineers, and distinguished engineers.
  • Foster collaboration across Central Engineering, Product Groups, and external partners.
  • Influence long-term semiconductor technology and platform strategy.

Benefits

  • Competitive benefits package alongside salary.
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