Senior DFT Logic Design Engineer

Intel•Chandler, AZ

2d•$141,910 - $269,100•Hybrid

About The Position

The Senior DFT Logic Design Engineer provides technical support to Intel Foundry Services customers on our PDKs, DFT/DFM insertion, ATPG validation methodology and flows. The successful candidate will collaborate with internal teams across Intel and external stakeholders such as foundry customers' design teams, IP providers, and EDA vendors on issue resolution. They will create content, application notes and deliver technical training/presentations. This role drives the quality of ASIC DFT/DFM and ATPG validation methodology, capability/flow and documentation for block level and SOC level. The engineer will also support and provide Tool/Flow/Methodology on customer issues and challenges for successful customer tape-outs, and to increase customer satisfaction.

Requirements

US Citizenship required.
Ability to obtain a US Government Security Clearance.
Bachelor's degree in Electrical / Computer Engineering, Computer Science, or in a STEM related field of study.
3+ years of experience with advanced CMOS processes (16nm and below).
3+ years of experience in implementing ASIC DFT/DFM insertion (MBIST, LBIST, SCAN, JTAG, ...) at ASIC design block level and at full chip level.
Performing ATPG validation and DFT timing and DFT signoff at SOC level.
4+ years of experience in one or more of the following scripting languages e.g. Python, Perl, Tcl, and/or shell scripting.
Customer-oriented attitude and mindset.
Self-driven and results-oriented, capable of effectively working multiple tasks.
Team player - effective team-work skillset to drive and find solutions for customer design implementation issues/challenges.
Analytical problem-solving skills.
Effective communication skills, as well as experience in collaboration, listening and providing feedback.

Nice To Haves

Active US Government Security Clearance with a minimum of Secret level.
Post Graduate degree in Electrical / Computer Engineering, Computer Science, or in a STEM related field of study.
Hands-on experience in one or more areas of Design Implementation and methodology - (ASIC design, Fullchip Integration, Design Signoff, LVS, DRC, DFX/DFM, Reliability, etc).
Experience using major EDA tools suites for MBIST insertion, hierarchical SCAN and JTAG insertion, DFT constraint generation and ATPG validation for single die and multi-die design.
Experience in building/developing quality DFT/DFX insertion flow and ATPG validation flow.
Experience in working with RTL and Hard IP designers on DFT/DFM implementation methodology.
Experience in working with physical designers on DFT/DFM physical implementation, validation, and DFT timing signoff.
Experience with providing technical direction to engineering teams, including but not limited to customer support, driving methodologies to streamline design work.
Customer facing experience.
Semiconductor foundry experience.

Responsibilities

Collaborate with internal teams across Intel and external stakeholders such as foundry customers' design teams, IP providers, and EDA vendors on issue resolution.
Create content, application notes and deliver technical training/presentations.
Drive quality of ASIC DFT/DFM and ATPG validation methodology, capability/flow and documentation for block level and SOC level.
Support and provide Tool/Flow/Methodology on customer issues and challenges for successful customer tape-outs, and to increase customer satisfaction.