Senior CAD Engineer – Physical Verification

Micron • Boise, ID

8d

About The Position

Micron Technology is seeking a Senior CAD Engineer focused on physical verification. The role develops and maintains physical verification tools, flows, and methodologies for DRAM, HBM, NAND, and emerging memory products. It develops, debugs, qualifies, and releases Siemens Calibre DRC and LVS rule decks using SVRF, translating process design rules into verification checks and defining the test cases, coverage criteria, and regression methods used to qualify them.

The engineer partners with process, design, layout, modeling, and verification teams to establish signoff strategies and resolve verification issues. The role guides design teams on verification methodologies, waivers, and debugging, and provides training, documentation, and production support. It also evaluates EDA technologies, automates verification setup, execution, and reporting—including AI-assisted analysis and debugging—and leads technical projects while contributing to the physical verification roadmap.

The estimated US base salary is $104,000–$221,000 per year. Additional compensation may include benefits, bonuses, and equity. Micron describes benefits including medical, dental, and vision plans, income-protection programs, paid family leave, paid time off, and paid holidays.

Requirements

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or Computer Science, or equivalent.
• At least 5 years of industry experience in CAD, EDA, or semiconductor design.
• Experience with DRC and LVS physical verification, IC layout, and process design rules.
• Ability to interpret design-rule requirements and resolve complex verification issues in production flows.
• Proficiency in Python and at least one additional language, such as SKILL, Tcl, Perl, C, or C++.
• Experience with Linux/Unix and shell scripting.
• Solid CMOS and VLSI fundamentals.
• Clear communication and practical debugging skills across global teams.

Nice To Haves

• Experience developing and qualifying Calibre DRC and LVS rule decks in SVRF, using nmDRC, nmLVS, and Results Viewing Environment (RVE).
• Knowledge of layout-dependent effects, electrical rule checking (ERC), programmable ERC (PERC), antenna checks, and density checks.
• Experience optimizing rule-deck coverage, runtime, and memory use.
• Experience with Cadence Virtuoso, SKILL, or Cadence physical verification tools.
• Experience applying AI/ML, large language models, or agentic AI to engineering workflows.
• Experience with source control, automated testing, and release management.
• Knowledge of DRAM, HBM, NAND, or emerging memory development.

Responsibilities

• Develop and maintain physical verification tools, flows, and methodologies for DRAM, HBM, NAND, and emerging memory products.
• Develop, debug, qualify, and release Siemens Calibre DRC and LVS rule decks using SVRF.
• Translate process design rules into verification checks and define test cases, coverage criteria, and regression methods for qualification.
• Partner with process, design, layout, modeling, and verification teams to define signoff strategies and resolve verification issues.
• Guide design teams on verification methodologies, waivers, and debugging.
• Provide training, documentation, and production support.
• Evaluate EDA technologies that improve verification quality, performance, and capacity.
• Automate verification setup, execution, and reporting, including AI-assisted analysis and debugging.
• Lead technical projects and contribute to the physical verification roadmap.

Benefits

• Choice of medical plans.
• Choice of dental plans.
• Choice of vision plans.
• Programs to help protect income in case of illness or injury.
• Paid family leave.
• Paid time off.
• Paid holidays.
• Additional compensation may include bonuses and equity.

What This Job Offers

• Job Type: Full-time
• Career Level: Senior