Simulation

Micron•Boise, ID

About The Position

Micron Technology is hiring a Senior CAD Engineer to develop and support CAD tools, automation, and production flows for custom IC design, layout, simulation, and verification. The role may focus on one or more areas, including layout automation, physical verification, circuit simulation, and digital implementation. It integrates and qualifies in-house and commercial EDA tools, works with design and process teams to solve workflow challenges, and evaluates tools and industry offerings to improve quality, performance, and efficiency. The engineer provides documentation, training, and production support, and applies AI/ML and agentic AI to CAD automation, debugging, and user support. The position also involves developing scalable software, mentoring engineers, leading technical projects, and contributing to CAD methodology roadmaps. This is a full-time position. The estimated US base salary is $104,000–$221,000 per year. Additional compensation may include benefits, bonuses, and equity. Micron describes benefits including medical, dental, and vision plans; income protection benefits; paid family leave; paid time off; and paid holidays.

Requirements

Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or Computer Science, or equivalent.
At least 5 years of industry experience in CAD, EDA, or semiconductor design.
Experience developing or supporting EDA tools and flows in at least one area: custom layout, physical verification, circuit simulation, or digital implementation.
Experience with IC design CAD tools for schematic capture, layout, simulation, or verification.
Proficiency in Python and at least one additional language, such as SKILL, Tcl, Perl, C, or C++.
Experience with Linux/Unix and shell scripting.
Solid CMOS and VLSI fundamentals.
Clear communication and practical debugging skills across global teams.

Nice To Haves

Experience with Cadence Virtuoso and SKILL, including layout automation or parameterized cell (PCell) development.
Experience with Calibre design rule checking (DRC) and layout versus schematic (LVS) flows, or rule-deck development in SVRF.
Experience with circuit simulators such as Spectre, HSPICE, FineSim, PrimeSim, VCS, or Xcelium.
Experience with RTL-to-GDS tools such as Fusion Compiler, Innovus, PrimeTime, or Formality.
Experience with parasitic extraction tools such as StarRC or Quantus.
Experience applying AI/ML, large language models, or agentic AI to engineering workflows.
Experience with source control, automated testing, and release management.
Knowledge of DRAM, HBM, NAND, or emerging memory development.

Responsibilities

Develop, enhance, and debug CAD tools, automation, and flows for custom IC design, layout, simulation, and verification.
Contribute to one or more functional areas: layout automation, physical verification, circuit simulation, or digital implementation.
Integrate, evaluate, and qualify in-house and commercial EDA tools in production environments.
Partner with design, layout, verification, and process teams to resolve workflow and tool-integration challenges.
Identify gaps in current tools and flows, and evaluate EDA industry offerings to improve quality, performance, and efficiency.
Provide training, documentation, and production support to end users.
Apply AI/ML and agentic AI to CAD automation, debugging, and user support.
Develop clean, scalable software and mentor engineers to support their technical growth.
Lead technical projects and contribute to CAD methodology roadmaps.