Senior Physical Verification CAD Engineer

Microsoft • Raleigh, NC

9d • $119,800 - $261,000

About The Position

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) powers Microsoft’s cloud infrastructure and supports its online businesses and Azure platform. The Senior Physical Verification CAD Engineer will drive Physical Verification CAD solutions for Microsoft silicon design teams, enabling and supporting advanced-node DRC, LVS, antenna, and ESD signoff flows. The role works closely with EDA vendors and internal design teams, owns PV signoff methodology end to end, identifies gaps, and delivers scalable, production-ready solutions across multiple silicon programs. The position also includes developing and deploying AI-enabled agents to automate and optimize Physical Verification and PERC workflows across the Silicon organization.

The role requires a doctorate and at least one year of technical engineering experience, a master’s degree and at least four years, a bachelor’s degree and at least five years, or equivalent experience. Candidates must meet Microsoft, customer, and/or government security screening requirements, including a Microsoft Cloud Background Check and verification of citizenship or other qualifying status for access to export-controlled information. The position is listed as Silicon Engineering IC4. The typical U.S. base pay range is $119,800–$234,700 per year; a different range applies in the San Francisco Bay Area and New York City metropolitan area, where it is $160,200–$261,000 per year. Certain roles may be eligible for benefits and other compensation. Applications are accepted on an ongoing basis until the position is filled, and the posting will remain open for at least five days.

Requirements

• Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or a related field and at least 1 year of technical engineering experience; or a master’s degree in one of these fields and at least 4 years of technical engineering experience; or a bachelor’s degree in one of these fields and at least 5 years of technical engineering experience; or equivalent experience.
• Ability to meet Microsoft, customer, and/or government security screening requirements, including the Microsoft Cloud Background Check upon hire or transfer and every two years thereafter.
• Provide proof of citizenship, U.S. residency, or other protected status for assessment of eligibility to access export-controlled information; citizenship will be verified with a valid passport, with other applicable documents accepted for lawful permanent residents, refugees, and asylees.

Nice To Haves

• Bachelor’s degree plus 7 years or master’s degree plus 5 years of relevant experience in Physical Verification, Physical Design, or CAD methodology roles.
• Strong hands-on experience with Physical Verification checks, including base and metal DRC, LVS, ERC, and antenna checks.
• Proficiency with industry-standard Physical Verification tools such as Calibre.
• Scripting proficiency in at least one language such as TCL, Python, Perl, or equivalent for flow automation, debugging, and data analysis.
• Ability to debug complex cross-domain issues, determine root cause across design, flow, or tool domains, and drive issues to closure across teams.
• SVRF rule or deck enablement experience, including customization and debugging support.
• Experience with advanced verification checks such as PERC (including custom or CNOD-based checks), ESD, EOS, level shifter, and reliability-focused verification.
• Exposure to shift-left PV methodologies, TCIC flows, and early-stage verification strategies that improve convergence and reduce late-stage surprises.
• Prior experience contributing to or leading PV, methodology councils, or multi-project enablement efforts.

Responsibilities

• Develop, maintain, and support Physical Verification flows across silicon projects, from early design (shift-left) through final signoff, including DRC, LVS, ERC, antenna, and advanced checks.
• Address PV-related flow and design issues, including tool stability, runtime scalability, deck integration, waiver correctness, and cross-tool debugging.
• Coordinate with CAD, Technology, and external EDA partners to communicate PV requirements, influence roadmap priorities, and unblock execution at critical project milestones.
• Support PDK and technology-node enablement, validating that PV flows are production-ready and aligned with foundry decks and internal signoff criteria across technology variants.
• Contribute training materials, documentation, onboarding labs, and continual improvements to automation and debugging infrastructure.
• Develop and deploy AI-enabled agents to automate and optimize PV and PERC workflows across the Silicon organization.

What This Job Offers

• Job Type: Full-time
• Career Level: Senior