Senior Physical Verification CAD Engineer

Microsoft • Mountain View, CA

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About The Position

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) develops infrastructure and foundational technologies supporting Microsoft’s online businesses and Azure platform. The Senior Physical Verification CAD Engineer will help drive advanced silicon signoff and physical verification at leading-edge technology nodes. The role develops and supports Physical Verification CAD solutions for Microsoft silicon design teams, enables advanced-node DRC, LVS, antenna, and ESD signoff flows, and works with EDA vendors and internal design teams. The engineer owns PV signoff methodology end to end, identifies gaps, and delivers scalable, production-ready solutions across silicon programs. The role also includes developing and deploying AI-enabled agents to automate and optimize PV and PERC workflows. This position requires Microsoft Cloud background screening and eligibility to access export-controlled information, with citizenship or qualifying status verified as a condition of employment.

Requirements

• Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or a related field and at least 1 year of technical engineering experience; or a master's degree in one of these fields and at least 4 years of technical engineering experience; or a bachelor's degree in one of these fields and at least 5 years of technical engineering experience; or equivalent experience.
• Ability to meet Microsoft, customer, and/or government security screening requirements, including passing the Microsoft Cloud Background Check upon hire or transfer and every two years thereafter.
• Ability to satisfy export-control access requirements by providing proof of citizenship, U.S. residency, or another protected status; citizenship must be verified with a valid passport, with other applicable documents accepted for lawful permanent residents, refugees, and asylees.

Nice To Haves

• Bachelor’s degree plus 7 years, or master’s degree plus 5 years, of relevant experience in Physical Verification, Physical Design, or CAD methodology roles.
• Strong hands-on experience with Physical Verification checks, including base and metal DRC, LVS, ERC, and antenna checks.
• Proficiency with industry-standard Physical Verification tools such as Calibre.
• Scripting skills in at least one language such as TCL, Python, Perl, or equivalent, for flow automation, debugging, and data analysis.
• Ability to debug complex cross-domain issues, identify root causes in design, flow, or tools, and drive issues to closure across teams.
• SVRF rule or deck enablement experience, including customization and debugging support.
• Experience with advanced verification checks such as PERC (including custom or CNOD-based checks), ESD, EOS, level shifter, and reliability-focused verification.
• Exposure to shift-left PV methodologies, TCIC flows, and early-stage verification strategies that improve convergence and reduce late-stage surprises.
• Prior experience contributing to or leading PV methodology councils or multi-project enablement efforts.

Responsibilities

• Develop, maintain, and support Physical Verification flows across silicon projects, from early design (shift-left) through final signoff, including DRC, LVS, ERC, antenna, and advanced checks.
• Address PV flow and design issues, including tool stability, runtime scalability, deck integration, waiver correctness, and cross-tool debugging.
• Align with CAD, Technology, and external EDA partners on PV requirements, influence roadmap priorities, and unblock execution at critical project milestones.
• Support PDK and technology-node enablement, validating that PV flows are production-ready and aligned with foundry decks and internal signoff criteria across technology variants.
• Contribute training materials, documentation, onboarding labs, and ongoing improvements to automation and debugging infrastructure.
• Develop and deploy AI-enabled agents to automate and optimize Physical Verification and PERC workflows across the Silicon organization.

What This Job Offers

• Job Type: Full-time
• Career Level: Senior