Senior CAD Engineer - Layout/Verification/Simulation
About The Position
Micron Technology is seeking a Senior CAD Engineer to develop, enhance, and debug CAD tools, automation, and flows for custom IC design, layout, simulation, and verification. The role contributes to one or more areas, including layout automation, physical verification, circuit simulation, and digital implementation. It also integrates, evaluates, and qualifies in-house and commercial EDA tools for production use. The engineer partners with design, layout, verification, and process teams to resolve workflow and tool-integration challenges; identifies gaps and evaluates industry EDA offerings to improve quality, performance, and efficiency; and provides training, documentation, and production support to users. The role applies AI/ML and agentic AI to CAD automation, debugging, and user support, develops scalable software, mentors engineers, leads technical projects, and contributes to CAD methodology roadmaps.
Requirements
- Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or Computer Science, or equivalent.
- At least 5 years of industry experience in CAD, EDA, or semiconductor design.
- Experience developing or supporting EDA tools and flows in custom layout, physical verification, circuit simulation, or digital implementation.
- Experience with IC design CAD tools for schematic capture, layout, simulation, or verification.
- Proficiency in Python and at least one additional language, such as SKILL, Tcl, Perl, C, or C++.
- Experience with Linux/Unix and shell scripting.
- Solid CMOS and VLSI fundamentals.
- Clear communication and practical debugging skills across global teams.
Nice To Haves
- Experience with Cadence Virtuoso and SKILL, including layout automation or parameterized cell (PCell) development.
- Experience with Calibre design rule checking (DRC) and layout versus schematic (LVS) flows, or rule-deck development in SVRF.
- Experience with circuit simulators such as Spectre, HSPICE, FineSim, PrimeSim, VCS, or Xcelium.
- Experience with RTL-to-GDS tools such as Fusion Compiler, Innovus, PrimeTime, or Formality.
- Experience with parasitic extraction tools such as StarRC or Quantus.
- Experience applying AI/ML, large language models, or agentic AI to engineering workflows.
- Experience with source control, automated testing, and release management.
- Knowledge of DRAM, HBM, NAND, or emerging memory development.
Responsibilities
- Develop, enhance, and debug CAD tools, automation, and flows for custom IC design, layout, simulation, and verification.
- Contribute to layout automation, physical verification, circuit simulation, or digital implementation.
- Integrate, evaluate, and qualify in-house and commercial EDA tools in production environments.
- Partner with design, layout, verification, and process teams to resolve workflow and tool-integration challenges.
- Identify gaps in current tools and flows and evaluate EDA industry offerings to improve quality, performance, and efficiency.
- Provide training, documentation, and production support to end users.
- Apply AI/ML and agentic AI to CAD automation, debugging, and user support.
- Develop clean, scalable software and mentor engineers.
- Lead technical projects and contribute to CAD methodology roadmaps.
Benefits
- Medical, dental, and vision plan options.
- Programs to help protect income in the event of illness or injury.
- Paid family leave.
- Paid time off.
- Paid holidays.
- Additional compensation may include bonuses and equity.
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What This Job Offers
Job Type
Full-time
Career Level
Senior
