Senior PDK Physical Verification Engineer

Intel•Hillsboro, OR

22h•Hybrid

About The Position

Join Intel's Design Technology Platform organization to develop and deploy advanced density-fill methodologies and Process Design Kit (PDK) solutions for advanced technology nodes and product designs. The role works across process technology, physical verification, and design automation to address manufacturability challenges, improve design productivity, and enable new technologies. The engineer will develop and validate density-fill solutions and algorithmic methodologies using industry-standard physical verification platforms. The role collaborates with process integration teams, design-rule owners, product design engineers, customers, and external EDA vendors. It also drives automation, develops validation and qualification frameworks, and creates technical documentation and training. As a technical expert, the engineer contributes to strategic initiatives shaping Intel's design-enablement roadmap. The position is based at an Intel site in Hillsboro, Oregon, with additional listed locations in Phoenix, Santa Clara, and Austin. It is eligible for Intel's hybrid work model, splitting time between the assigned Intel site and off-site. The posting describes an experienced-hire role and Shift 1. Intel offers competitive pay, stock bonuses, and health, retirement, and vacation benefit programs. The stated annual US salary range is $149,600–$284,580, with pay determined by location and other job-related factors.

Requirements

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field and 6+ years of relevant experience; or a master's degree and 5+ years of experience; or a PhD and 2+ years of experience.
4+ years of hands-on experience with at least one industry-standard physical verification platform, such as Calibre, ICV, or Pegasus, including methodology development, rule-deck debugging, validation, or production deployment.
3+ years of experience developing, maintaining, or debugging physical verification rule decks using SVRF, TVF, PXL, PVL, or Tcl-based verification environments.
Experience with semiconductor process technology, device physics, design rules, and manufacturability requirements.
Experience developing algorithmic solutions for physical-design and manufacturing challenges at advanced technology nodes.
Experience with Unix/Linux operating systems and engineering computing environments.
Excellent communication and technical presentation skills, including the ability to translate complex technical concepts into actionable solutions.
Strong problem-solving, debugging, and analytical skills.
Strong understanding of technology-scaling challenges and their effects on physical verification and design-rule development.

Nice To Haves

4+ years of direct experience developing, deploying, or supporting density-fill methodologies for advanced semiconductor technologies at 16nm and below.
Expertise in fill-rule implementation, density optimization, and manufacturing-driven design methodologies.
Deep experience with physical verification flows, including DRC, density analysis, fill verification, and process-aware design enablement.
Experience supporting or developing solutions for leading foundry, IDM, or advanced-process technologies.
Familiarity with custom layout environments such as Cadence Virtuoso or Synopsys Custom Designer.
Experience collaborating across multidisciplinary engineering teams and external partners to deliver solutions.
Experience leading technical initiatives, driving process improvements, or influencing product and methodology roadmaps.
Prior experience with semiconductor foundries, IDMs, OSATs, or EDA vendors developing physical verification methodologies, density-fill solutions, PDKs, or design-for-manufacturing technologies.

Responsibilities

Lead development, implementation, and validation of density-fill solutions within advanced PDKs.
Develop algorithmic solutions using physical verification platforms such as Calibre, Synopsys ICV, and Cadence Pegasus to ensure density compliance and manufacturability.
Collaborate with process integration teams, design-rule owners, product design engineers, and customers to define requirements and deliver solutions.
Drive automation initiatives to improve engineering efficiency, scalability, and deployment across design environments.
Design and develop validation frameworks, test suites, and qualification methodologies for tool and rule-deck releases.
Advance physical verification methodologies to address challenges associated with technology scaling.
Partner with external EDA vendors to influence and deploy next-generation tool capabilities and methodologies.
Develop technical documentation, training materials, and best practices for Intel's design community.
Serve as a technical expert and contribute to strategic initiatives shaping Intel's design-enablement roadmap.