PDK Testsite Engineer

Computer Task Group, Inc•UNAVAILABLE, UNAVAILABLE

1d•Remote

About The Position

CTG is hiring a remote PDK Testsite Engineer for a six-month position supporting a client. The engineer will design and develop semiconductor testsites, test chips, and device-level structures for process technology characterization and Process Design Kit (PDK) development. The role includes creating and modifying layouts with Cadence Virtuoso or comparable EDA tools, translating characterization and device-modeling requirements into silicon-ready layouts, and performing physical verification such as DRC and LVS. The engineer will support testsite development from design and verification through tapeout preparation and silicon characterization. Responsibilities also include analyzing electrical measurement and silicon test results; supporting PDK components such as device definitions, PCells, technology files, models, and verification flows; automating workflows with scripts; troubleshooting layout, PDK, verification, and EDA tool issues; documenting engineering work; and collaborating across process development, device modeling, design enablement, layout, CAD/EDA, test, and manufacturing teams. A bachelor's degree in Electrical Engineering, Computer Engineering, Microelectronics, Physics, or a related technical discipline is requested, or equivalent relevant experience. Excellent verbal and written English communication skills and professional interaction with a diverse group are required. The expected base salary is $72.00–$74.00 per hour. A competitive benefit package is also offered.

Requirements

Proficiency with Cadence Virtuoso or similar integrated circuit design and physical layout tools.
Understanding of semiconductor devices, fabrication processes, physical layout, and technology characterization.
Knowledge of semiconductor design rules, DRC/LVS, and physical verification methodologies.
Ability to translate technology specifications and characterization requirements into functional test structures.
Strong analytical, troubleshooting, debugging, and problem-solving skills.
Ability to interpret electrical measurement results and support silicon-level analysis.
Experience with PDK development, validation, or related semiconductor design enablement activities.
Strong technical documentation and cross-functional communication skills.
Experience developing semiconductor test structures, testsites, test chips, physical layouts, or PDK components.
Experience using Cadence Virtuoso or comparable IC design and layout tools.
Experience with semiconductor design rule implementation and physical verification.
Bachelor's degree in Electrical Engineering, Computer Engineering, Microelectronics, Physics, or a related technical discipline, or equivalent relevant experience.
Excellent verbal and written English communication skills and the ability to interact professionally with a diverse group.

Nice To Haves

Experience with Cadence SKILL programming, Python, Tcl, or similar scripting languages.
Experience developing PCells, layout automation, or verification workflows.
Familiarity with Synopsys IC Validator (ICV), Siemens Calibre, or comparable physical verification tools.
Experience with PDK development and validation, advanced semiconductor technology nodes, device characterization, or electrical measurement techniques.
Experience supporting test structures or test chips through design verification and tapeout.

Responsibilities

Design and develop semiconductor testsites, test chips, and device-level structures for process technology characterization and PDK development.
Create and modify physical layouts using Cadence Virtuoso or comparable EDA tools.
Translate process characterization and device-modeling requirements into test structures and silicon-ready layouts.
Interpret semiconductor design rules, technology ground rules, and layout specifications.
Perform and debug physical verification, including DRC and LVS.
Support testsite development through design, verification, tapeout preparation, and silicon characterization.
Analyze electrical measurement and silicon test results to identify device, interconnect, process, and design issues.
Support development and validation of PDK components, including device definitions, PCells, technology files, models, and verification flows.
Develop and maintain scripts to automate testsite generation, layout, verification, and data-processing workflows.
Troubleshoot layout, PDK, physical verification, and EDA tool issues.
Document testsite designs, verification methodologies, results, and engineering findings.
Collaborate with process development, device modeling, design enablement, layout, CAD/EDA, test, and manufacturing teams.