Mixed Signal Engineer

Apple•Austin, TX

About The Position

Apple Inc. is hiring an RF/Analog/Mixed Signal Engineer in Austin, Texas. The role involves designing and verifying high-speed, low-power analog and mixed-signal circuits and communication systems, from block and chip-level specifications through transistor-level design and testing. The engineer will use Virtuoso and SERDES systems to develop and assess circuit designs, and will perform block-level simulations and analyses against performance, power, and area requirements. The position includes designing clock distribution and clock-and-data recovery (CDR) circuits, investigating power-efficient clocking architectures, and designing and optimizing duty-cycle correctors and phase interpolators. Work also includes designing a 100 MHz reference clock receiver with minimal jitter contribution, implementing a 50-ohm termination, and addressing receiver headroom issues related to a power-supply reduction from 1.2 V to 1.06 V. The engineer will test chips across process, temperature, and voltage conditions to evaluate robustness and functionality. The position is 40 hours per week.

Requirements

Master's degree or foreign equivalent in Electrical Engineering, Computer Engineering, Electronics Engineering, or a related field.
Experience designing and analyzing high-speed analog and mixed-signal building blocks, including PLL, LDO, ADC, DAC, and phase interpolator.
Experience with end-to-end SERDES systems, including TX/RX design, channel characteristics, and equalization techniques.
Experience using RTL/Verilog modeling to develop mixed-signal block models for system-level design verification.
Experience using MATLAB to analyze SERDES performance, including jitter tolerance and equalization.
Experience using spectrum analyzers, oscilloscopes, and signal generators for post-silicon validation and testing.
Experience with analog and high-speed circuit layout techniques, including matching and noise considerations, to ensure post-layout performance.
Experience applying signal processing to design and analysis, including filtering, equalization, and spectral analysis.
Experience using Python and Shell scripting to automate design simulations and perform data analysis.
Experience with design validation tools, including EMIR, static timing analysis, and DFT, to ensure design robustness and manufacturability.

Responsibilities

Generate and document block- and chip-level specifications, aligning functional and performance requirements with system-level goals for high-speed, low-power communication.
Design complex analog and mixed-signal circuits at the transistor level while meeting power, performance, and area constraints; use Virtuoso to test designs under different options and environments.
Conduct block-level simulations and analyses to verify functionality and evaluate performance, power, and area requirements.
Design clock distribution circuits and CDR circuits, using SERDES systems to determine required circuits and recover data with minimal error.
Investigate clocking architectures that reduce power consumption.
Design and optimize duty-cycle correctors and phase interpolators, including precise comparators and samplers for the DCC and layout optimization.
Improve phase-interpolator linearity and step size within the CDR block to enhance performance and reduce power consumption.
Design a 100 MHz reference clock receiver that delivers the clock from the pad to the PLL with minimal jitter contribution.
Design a 50-ohm termination to avoid chip reflections and address receiver headroom degradation associated with reducing the supply voltage from 1.2 V to 1.06 V.
Test chips under varying process, temperature, and voltage conditions to assess robustness and functionality.