Analog Mixed-Signal SystemVerilog Modeling Engineer

Cynet Systems • San Jose, CA

1d

About The Position

The engineer will build behavioral SystemVerilog models of analog and mixed-signal circuits, including PLLs, clocking, ADC/DAC, TX/RX analog front ends, and calibration loops. The models will be integrated into a SystemVerilog UVM verification environment for high-speed SerDes and SoC IP. The role involves close collaboration with analog circuit designers, RTL designers, and verification engineers, and leading and participating in modeling and verification of leading-edge designs in advanced CMOS processes.

Requirements

• Hands-on experience writing behavioral models of analog circuits in SystemVerilog.
• Working knowledge of analog and mixed-signal circuit fundamentals.
• Working knowledge of the SystemVerilog UVM methodology.
• Proven skill debugging simulation failures and waveforms.

Nice To Haves

• Familiarity with high-speed interface standards.

Responsibilities

• Read schematics, netlists, and circuit specifications to define model requirements.
• Develop model architecture and accuracy targets while balancing accuracy against simulation speed.
• Write behavioral SystemVerilog models of analog blocks.
• Validate models against transistor-level simulation results.
• Debug simulation failures and identify root causes in the model, RTL, or testbench.
• Document model behavior, limitations, and interfaces.
• Lead and participate in modeling and verification of leading-edge designs in advanced CMOS processes.

What This Job Offers

• Job Type: Full-time
• Education Level: No Education Listed