Senior Analog and Mixed Signal Design Engineer

Intel Corporation•Santa Clara, CA

2d•$141,910 - $269,100•Onsite

About The Position

Intel’s Advanced Design Foundational IP Organization (AD-FIP) within Design Technology Platform (DTP) develops analog/mixed-signal and high-speed I/O IP. The High-Speed I/O team creates SerDes and die-to-die interface reference designs and test chips that co-optimize Intel process technology with next-generation wireline standards, including high-speed PAM4 electrical links, PCIe, UCIe, and HBM. This senior individual-contributor role seeks a technical expert in high-speed SerDes circuit design and system architecture. The engineer will own SerDes link architecture on Intel leading-technology test chips, from link budgeting and equalization strategy through transistor-level design of critical analog front-end and clocking blocks. The role also translates link requirements into device, interconnect, and design-rule requirements that help shape future Intel process nodes, and provides technical leadership across design, layout, and measurement engineers.

Requirements

Bachelor’s degree in Electrical Engineering, Computer Engineering, or Electrical and Computer Engineering plus 6 or more years of industry experience in high-speed wireline SerDes circuit design; or a master’s degree in one of these fields plus 4 or more years; or a Ph.D. in one of these fields plus 2 or more years.
Experience with transistor-level design of SerDes TX, RX, or clocking circuits in at least one silicon-proven design at 28 Gb/s per lane or higher.
Experience in at least one of the following: SerDes link architecture involving channel and link-budget analysis or equalization trade-off studies used to set block-level specifications; lab validation of high-speed links involving BER, eye, or jitter measurement and simulation correlation; or behavioral/statistical link modeling in MATLAB or Python.

Nice To Haves

Experience with silicon-proven designs at 56 Gb/s PAM4 or higher in FinFET or GAA CMOS, and multiple tape-outs with block ownership.
Experience across SerDes architecture, lab validation, and link modeling.
Experience in ADC/DSP-based receivers at 112 Gb/s PAM4 or higher, including time-interleaved ADC design.
Experience in 224 Gb/s-class link development, including IEEE 802.3dj or OIF CEI-224G.
Experience in PCIe Gen6/Gen7 PHY or UCIe die-to-die PHY development.
Design experience on 5nm-class or more advanced nodes and design-technology co-optimization with process teams.
Experience in package and channel co-design, including package/PCB channel modeling, signal and power integrity, and crosstalk.
First-author publications at ISSCC, VLSI Symposium, CICC, or JSSC, or patents in SerDes circuits or architecture.
Technical leadership of a multi-engineer SerDes design team through a full PHY delivery.

Responsibilities

Define SerDes link architecture for next-generation interfaces, including 224G/448G-class PAM4 electrical links, PCIe Gen7/Gen8, and UCIe; conduct channel analysis, link budgeting, jitter and noise budgeting, and equalization partitioning across TX FFE, RX CTLE, DFE, and ADC/DSP-based receivers.
Build and maintain statistical and time-domain system-level link models in MATLAB or Python, including COM- and IBIS-AMI-based models, and derive block-level specifications for TX, RX, ADC, and clocking circuits.
Lead transistor-level design of critical SerDes blocks, including TX drivers with FFE, RX AFE, DFE and slicers, time-interleaved ADC front ends, CDR and phase interpolators, LC and ring PLLs, and clock distribution.
Drive test-chip definition, integration, tapeout readiness, and silicon bring-up; correlate measured BER, eye, jitter, and power against models, and lead root-cause analysis of silicon-to-model gaps.
Translate SerDes requirements into process and PDK requirements, including device fT/fmax and parasitics, BEOL RC, inductor Q, matching, ESD capacitance budget, reliability, and aging; drive design-technology co-optimization with process, PDK, and template-library teams.
Mentor engineers, lead design reviews, and represent Intel Foundry in technical engagements with IP partners and foundry customers.