Senior Analog and Mixed Signal Design Engineer

Intel•Hillsboro, OR

1d•Onsite

About The Position

Intel’s Advanced Design Foundational IP Organization within the Design Technology Platform develops analog/mixed-signal and high-speed I/O IP for Intel process technologies. The High-Speed I/O team develops SerDes and die-to-die interface reference designs and test chips, co-optimizing process technology with wireline standards such as high-speed PAM4 links, PCIe, UCIe, and HBM. This senior individual-contributor role seeks an expert in high-speed SerDes circuit design and system architecture. The engineer will own SerDes link architecture for Intel technology test chips, spanning link budgets and equalization strategies through transistor-level design of critical analog front-end and clocking blocks. The role also translates link requirements into device, interconnect, and design-rule requirements for future process nodes, and provides technical leadership across design, layout, and measurement engineers.

Requirements

Bachelor’s degree in Electrical Engineering, Computer Engineering, or Electrical and Computer Engineering and at least 6 years of industry experience in high-speed wireline SerDes circuit design; or a master’s degree in one of these fields and at least 4 years of relevant industry experience; or a Ph.D. in one of these fields and at least 2 years of relevant industry experience.
Experience with transistor-level design of SerDes TX, RX, or clocking circuits in at least one silicon-proven design at 28 Gb/s per lane or higher.
Experience in at least one of the following: SerDes link architecture, including channel and link-budget analysis or equalization trade-off studies used to set block-level specifications; laboratory validation of high-speed links, including BER, eye, or jitter measurement and simulation correlation; or behavioral or statistical link modeling in MATLAB or Python.

Nice To Haves

Experience with silicon-proven designs at 56 Gb/s PAM4 or higher in FinFET or GAA CMOS, and multiple tape-outs with block ownership.
Experience across SerDes architecture, laboratory validation, and link modeling.
Experience in ADC/DSP-based receivers at 112 Gb/s PAM4 or higher, including time-interleaved ADC design.
Experience developing 224 Gb/s-class links, including IEEE 802.3dj or OIF CEI-224G.
Experience developing PCIe Gen6/Gen7 PHY or UCIe die-to-die PHY.
Design experience on 5nm-class or more advanced nodes and design-technology co-optimization with process teams.
Experience in package and channel co-design, including package/PCB channel modeling, signal and power integrity, and crosstalk.
First-author publications at ISSCC, VLSI Symposium, CICC, or JSSC, or patents in SerDes circuits or architecture.
Technical leadership of a multi-engineer SerDes design team through full PHY delivery.

Responsibilities

Define SerDes link architecture for next-generation interfaces, including channel analysis, link budgets, jitter and noise budgets, and equalization partitioning across TX FFE, RX CTLE, DFE, and ADC/DSP-based receivers.
Build and maintain statistical and time-domain system-level link models in MATLAB or Python, including COM- and IBIS-AMI-based models, and derive block-level specifications for TX, RX, ADC, and clocking circuits.
Lead transistor-level design of critical SerDes blocks, including TX drivers with FFE, RX analog front ends, DFE and slicers, time-interleaved ADC front ends, CDR and phase interpolators, PLLs, and clock distribution.
Drive test-chip definition, integration, tapeout readiness, and silicon bring-up; compare measured BER, eye, jitter, and power against models and lead root-cause analysis of silicon-to-model gaps.
Translate SerDes requirements into process and PDK requirements, including device performance and parasitics, BEOL RC, inductor Q, matching, ESD capacitance budget, reliability, and aging.
Drive design-technology co-optimization with process, PDK, and template-library teams.
Mentor engineers, lead design reviews, and represent Intel Foundry in technical engagements with IP partners and foundry customers.