Process Integration Development Engineer - Defect Metrology

Intel•Hillsboro, OR

7h•Hybrid

About The Position

Intel’s Logic Technology Development (LTD) organization develops semiconductor process technologies that advance computing and extend Moore’s law. Defect Metrology supports this work by helping move technologies from research to high-volume manufacturing while maintaining quality. Within Manufacturing Integration Engineering, this role identifies defects affecting yield and performance, characterizes processes with metrology tools, investigates root causes, and develops defect-reduction roadmaps. The engineer works with process module and integration teams to develop and qualify process fixes using Model-Based Problem Solving (MBPS), and responds to defect baseline shifts with root-cause isolation and preventative actions consistent with 8D methodology. The role owns a process segment’s defect-metrology strategy, supports New Product Introduction, and helps meet yield objectives using metrology tools and test vehicles. It also involves presenting defect summaries, collaborating with integration, yield, and failure-analysis teams, and promoting accountability and a culture of trust, collaboration, safety, and quality. The position is based in Hillsboro, Oregon, and is eligible for Intel’s hybrid work model.

Requirements

Master’s degree in Materials Science and Engineering, Electrical Engineering, Chemical Engineering, Mechanical Engineering, Physics, Nuclear Engineering, Optics, Chemistry, or Computer Science.
Hands-on experimental research experience designing and conducting experiments, operating laboratory equipment for characterization, fabrication, or synthesis, and analyzing statistical data.
Strong data-analysis and problem-debugging skills.
Ability to work as a team player with flexibility and adaptability to changing business needs.
Strong ownership mindset and ability to drive problems to closure.
Excellent communication and navigation skills with larger audiences.

Nice To Haves

Academic research, coursework, laboratory, or internship experience with materials characterization (such as SEM, TEM, or AFM), materials fabrication, synthesis, metrology, or statistical/data analysis using tools such as MATLAB, Excel, JMP, or Python.
Knowledge of semiconductor processing fundamentals, including lithography, wet or dry etch, chemical mechanical polishing, and thin films; semiconductor or transistor device physics; and Design of Experiments (DOE).
Experience with defect metrology, defect inspection or improvement, yield analysis, or process integration.
Demonstrated application of Statistical Process Control (SPC) or Design of Experiments (DOE) principles.
Experience with complex problem-solving methodologies such as root-cause analysis, Model-Based Problem Solving (MBPS), 5 Why, Fishbone diagrams, or 8D frameworks.
Understanding of semiconductor physics or semiconductor-processing cleanroom unit operations.
Understanding of defect metrology tools such as brightfield, darkfield, or voltage contrast (VC).

Responsibilities

Own a process segment and ensure adequate metrology is in place to detect and respond to yield-limiting defects before end-of-line sort.
Investigate exclusionary baseline shifts and restore segment defect health to a capable, demonstrated baseline.
Develop new recipes and RFCs as part of New Product Introduction (NPI).
Provide navigation and leadership toward Intel’s yield objectives using metrology tools and test vehicles, including QTM and Short Loop.
Organize and present defect summaries to F25, LTD, and MDCE engineering teams.
Partner with Intel Integration, Yield, and failure-analysis laboratories to identify root causes of defect issues.
Hold collaborators accountable for quality through Integrated Module Team (IMT) and Focus Team (FT) forums.
Collaborate with the LTD Defect Metrology group and other LTD teams.
Model and foster a team culture of trust, collaboration, safety, accountability, and sustained excellence.
Build strong relationships with other LTD teams based on mutual trust and respect.