Process Integration Development Engineer - Defect Metrology

Intel•Hillsboro, OR

13h•Hybrid

About The Position

Intel’s Logic Technology Development organization develops advanced semiconductor process technologies that extend Moore’s Law. Within Manufacturing Integration Engineering, the Defect Metrology Engineer identifies defects that affect yield and performance, characterizes processes using metrology tools, investigates root causes, and develops defect-reduction roadmaps. The engineer works with process module and integration teams to develop and qualify process fixes using Model-Based Problem Solving (MBPS), and responds to defect baseline shifts with root-cause isolation and preventative actions consistent with 8D methodology. The role contributes to the development of future process technologies and the transition from research to high-volume manufacturing while maintaining quality standards. The position owns a segment of the process and ensures metrology detects yield-limiting defects before end-of-line sort. It involves developing recipes and RFCs for New Product Introduction, using metrology tools and test vehicles to support yield objectives, presenting defect summaries to engineering teams, and partnering with integration, yield, and failure-analysis groups. The engineer also promotes accountability, collaboration, safety, and quality across teams. The role is based in Hillsboro, Oregon, and uses Intel’s hybrid work model, with time split between the assigned site and off-site.

Requirements

PhD in Computer Science, Physics, Materials Science and Engineering, Chemical Engineering, Electrical Engineering, Mechanical Engineering, Nuclear Engineering, Optics, or Chemistry with a focus on hands-on experimental research.
Strong data-analysis and problem-debugging skills.
Ability to work as a team player with flexibility and adaptability to changing business needs.
Strong ownership mindset and ability to drive problems to closure.
Excellent communication and navigation skills when working with larger audiences.
Understand and adhere to Intel cultural values, including Customer First, Fearless Innovation, Results Driven, One Intel, Integrity, Quality, and Inclusion.

Nice To Haves

At least 1 year of experience in one or more of the following: experimental research; designing and conducting experiments; operating characterization, fabrication, or synthesis equipment; or statistical data analysis.
Experience with materials characterization (such as SEM or TEM), materials fabrication or synthesis, metrology, or statistical/data analysis tools such as MATLAB, Excel, or JMP.
Knowledge of semiconductor processing fundamentals, including lithography, wet or dry etch, and chemical or mechanical polishing; semiconductor or transistor device physics; or design of experiments.
Experience in defect metrology, defect improvement, yield improvement, or process integration.
Experience with Statistical Process Control (SPC) or Design of Experiments (DOE) principles.
Experience with complex problem-solving methods such as root-cause analysis, MBPS, 5 Why, or Fishbone.
Understanding of semiconductor physics or semiconductor processing.
Understanding of defect metrology tools such as brightfield, darkfield, or voltage contrast (VC).

Responsibilities

Own a process segment and ensure adequate metrology is in place to detect and respond to yield-limiting defects before end-of-line sort.
Investigate and respond to exclusionary baseline shifts to restore segment defect health to a capable, demonstrated baseline.
Develop new recipes and RFCs as part of New Product Introduction (NPI).
Provide navigation and leadership toward Intel yield objectives using state-of-the-art metrology tools and test vehicles, including QTM and Short Loop.
Organize and present defect summaries to F25, LTD, and MDCE engineering teams.
Partner with Intel Integration, Yield, and failure-analysis labs to determine root causes of defect issues.
Hold team members and collaborators accountable for quality through Integrated Module Team (IMT) and Focus Team (FT) forums.
Collaborate as part of the LTD Defect Metrology group and build strong relationships with other LTD teams.
Model and foster a culture of trust, collaboration, safety, accountability, and sustained excellence.