Process Integration Development Engineer - Defect Metrology

Intel Corporation•Hillsboro, OR

1d•$115,110 - $219,550•Hybrid

About The Position

Intel’s Logic Technology Development (LTD) organization develops semiconductor manufacturing processes and advances technology scaling. Defect Metrology supports silicon process development by identifying yield- and performance-impacting defects, characterizing processes with metrology tools, determining root causes, and developing defect-reduction roadmaps. The role works with process module and integration teams to develop and qualify process fixes using Model-Based Problem Solving (MBPS), and responds to defect-trend shifts with preventative actions consistent with 8D methodology. The position supports Intel’s F25 processes and contributes to moving technologies from research toward high-volume manufacturing while meeting quality and program milestones. The engineer owns a process segment’s defect-metrology strategy, data collection and quality, and response to defect-trend changes. The role develops recipes and response plans for New Product Introduction, uses metrology tools and test vehicles to support yield objectives, communicates defect status to engineering teams, and partners with integration, yield, and failure-analysis teams to identify root causes. The position also promotes accountability, collaboration, safety, and quality across the team. The role is based in Hillsboro, Oregon, and is eligible for Intel’s hybrid work model, splitting time between the assigned site and off-site. It is an experienced-hire position on Shift 1. The posted annual US salary range is $115,110–$219,550; individual compensation depends on location and other factors.

Requirements

Master’s degree with at least 3 years of experience, or PhD with at least 1 year of experience, in Computer Science, Physics, Material Science and Engineering, Chemical Engineering, Electrical Engineering, Mechanical Engineering, Nuclear Engineering, Optics, or Chemistry focused on hands-on experimental research.
At least 1 year of experience in experimental research, including designing and conducting experiments, operating characterization, fabrication, or synthesis equipment, and analyzing statistical data.
At least 1 year of experience in materials characterization (such as SEM or TEM), materials fabrication or synthesis, metrology, and statistical or data analysis using tools such as MATLAB, Excel, or JMP.
At least 1 year of experience with semiconductor processing fundamentals, including lithography, wet or dry etch, and chemical or mechanical polishing; semiconductor or transistor device physics; and design of experiments.
At least 1 year of experience with complex problem-solving methodologies such as root cause analysis, MBPS, 5 Why, or Fishbone.
Strong data-analysis and problem-solving skills.
Ability to work as a team player with flexibility and adaptability to changing business needs.
Strong ownership mindset and ability to drive problems to closure.
Excellent communication and navigation skills with larger audiences.
Understand and adhere to Intel cultural values, including Customer First, Fearless Innovation, Results Driven, One Intel, Integrity, Quality, and Inclusion.

Nice To Haves

At least 1 year of experience in defect metrology, defect improvement, yield improvement, or process integration.
Experience with Statistical Process Control (SPC) or Design of Experiments (DOE) principles.
Expertise in semiconductor physics or semiconductor processing.
Expertise with defect metrology tools such as brightfield, darkfield, or voltage contrast (VC).

Responsibilities

Own a process segment to ensure adequate metrology detects and responds to yield-limiting defects before end-of-line sort.
Manage data collection strategies, data integrity, and quality for metrology scans in the segment.
Investigate and respond to exclusionary baseline shifts and restore segment defect health to a capable, demonstrated baseline.
Develop new recipes and response action plans as part of New Product Introduction (NPI).
Provide navigation and leadership toward yield objectives using state-of-the-art metrology tools and test vehicles, including QTM and Short Loop.
Organize and present defect summaries to F25, LTD, and MDCE engineering teams.
Partner with Intel Integration, Yield, and failure-analysis labs to identify root causes of defect issues.
Hold collaborators accountable for quality through Integrated Module Team (IMT) and Focus Team (FT) forums.
Collaborate as part of the LTD Defect Metrology group and build relationships with other LTD teams based on mutual trust and respect.
Model and establish a team culture of trust, collaboration, safety, accountability, and sustained excellence.
Develop and qualify process fixes with process module and integration teams using Model-Based Problem Solving (MBPS).
Implement preventative actions consistent with 8D methodology.