Process Integration Development Engineer - Defect Metrology

Intel Corporation•Hillsboro, OR
•$99,030 - $139,810•Hybrid

About The Position

Intel’s Logic Technology Development (LTD) organization develops advanced semiconductor process technologies and supports their progression from research to high-volume manufacturing. Within Manufacturing Integration Engineering, Defect Metrology engineers identify and characterize defects that affect yield and performance, and develop plans to reduce them to best-in-class targets. The engineer will use advanced metrology tools to characterize processes, investigate defect root causes, and develop defect-reduction roadmaps tied to program milestones. They will partner with process module and integration teams to develop and qualify fixes using Model-Based Problem Solving (MBPS), and respond to defect baseline shifts by isolating root causes and implementing preventative actions consistent with 8D methodology. The role is based in Hillsboro, Oregon, and is eligible for Intel’s hybrid work model, splitting time between the assigned site and off-site work.

Requirements

  • Master’s degree in Materials Science and Engineering, Electrical Engineering, Chemical Engineering, Mechanical Engineering, Physics, Nuclear Engineering, Optics, Chemistry, or Computer Science.
  • Hands-on experimental research experience, including designing and conducting experiments, operating laboratory equipment for characterization, fabrication, or synthesis, and analyzing statistical data.
  • Strong data-analysis and problem-debugging skills.
  • Ability to work as a team player with flexibility and adaptability to changing business needs.
  • Strong ownership mindset and ability to drive issues to closure.
  • Excellent communication and navigation skills when addressing larger audiences.
  • Understand and adhere to Intel cultural values, including Customer First, Fearless Innovation, Results Driven, One Intel, Integrity, Quality, and Inclusion.

Nice To Haves

  • Academic research, coursework, laboratory, or internship experience in materials characterization (such as SEM, TEM, or AFM), materials fabrication, synthesis, metrology, or statistical/data analysis using MATLAB, Excel, JMP, or Python.
  • Knowledge of semiconductor processing fundamentals, including lithography, wet or dry etch, chemical mechanical polishing, and thin films; semiconductor or transistor device physics; and Design of Experiments (DOE).
  • Experience with defect metrology, defect inspection or improvement, yield analysis, or process integration.
  • Demonstrated application of Statistical Process Control (SPC) or Design of Experiments (DOE) principles.
  • Experience with complex problem-solving methods, including root-cause analysis, Model-Based Problem Solving (MBPS), 5 Why, Fishbone diagrams, or 8D frameworks.
  • Understanding of semiconductor physics or semiconductor processing cleanroom unit operations.
  • Understanding of defect metrology tools such as brightfield, darkfield, or voltage contrast (VC).

Responsibilities

  • Own a process segment and ensure adequate metrology is in place to detect and respond to yield-limiting defects before end-of-line sort.
  • Investigate and respond to exclusionary baseline shifts to restore segment defect health to a capable, demonstrated baseline.
  • Develop new recipes and RFCs as part of New Product Introduction (NPI).
  • Provide navigation and leadership toward Intel yield objectives using state-of-the-art metrology tools and test vehicles, including QTM and Short Loop.
  • Organize and present defect summaries to F25, LTD, and MDCE engineering teams.
  • Partner with Intel Integration, Yield, and failure analysis labs to establish root causes for defect issues.
  • Hold the team and collaborators accountable for quality through Integrated Module Team (IMT) and Focus Team (FT) forums.
  • Work collaboratively within the LTD Defect Metrology group.
  • Model and establish a team culture of trust, collaboration, safety, accountability, and sustained excellence.
  • Build strong relationships with other LTD teams based on mutual trust and respect.
  • Characterize semiconductor processes, investigate defect root causes, and develop defect-reduction roadmaps.
  • Work with process module and integration teams to develop and qualify process fixes through Model-Based Problem Solving (MBPS), and implement preventative actions consistent with 8D methodology.

Benefits

  • Competitive pay
  • Stock bonuses
  • Health benefits
  • Retirement benefits
  • Vacation
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