Principal Silicon Product Engineer

Google•Sunnyvale, CA

5d•$281,000 - $391,000

About The Position

As Principal Silicon Product Engineer, you will serve as the chief technical authority for the Silicon Sourcing organization, bridging hardware engineering design, global manufacturing ecosystems, and strategic sourcing across the silicon lifecycle. You will lead technical evaluations across Custom Silicon (ASICs/COT, including TPUs, gSOC, custom networking and accelerators) and off-the-shelf silicon products such as GPUs, x86 CPUs, memory, storage, and strategic silicon. You will work across the silicon product lifecycle, from architecture and process-node selection through NPI, DFM/DFT validation, wafer-fab yield modeling, advanced-packaging integration, and test-engineering optimization. As a technical partner to Platforms Engineering, Systems Architecture, and Cloud Supply Chain Operations, you will translate semiconductor physics and manufacturing realities into sourcing leverage, risk mitigation, and performance improvements. You will engage with foundries, merchant silicon vendors, OSATs, and material suppliers. The role includes establishing technical should-cost foundations, evaluating cutting-edge process nodes, de-risking heterogeneous packaging, and defining yield and test parameters to optimize total cost of ownership.

Requirements

15 years of relevant experience in Semiconductor Product Engineering, Silicon Architecture, Foundry Engineering, or Technical Sourcing Engineering.
Experience with the semiconductor product lifecycle, including design tape-out, wafer-fab processing, parametric yield analysis, advanced packaging/assembly, and high-volume test engineering (ATE/SLT).
Experience evaluating and scaling leading-edge nodes, including 3nm, 2nm, and beyond, and heterogeneous packaging technologies such as 2.5D/3D, CoWoS, chiplets, and HBM.
Experience covering both Custom ASIC/COT flows and standardized high-performance-compute silicon, including GPUs, x86/ARM CPUs, high-speed networking, and memory architectures.

Nice To Haves

Master’s degree or Ph.D. in Electrical Engineering, Microelectronics, Materials Science, or a related technical field.
Experience with silicon execution vehicles (eTV/mTV), silicon-photonics integration, advanced cooling/thermal interfaces, and custom AI-accelerator hardware bottlenecks.

Responsibilities

Serve as the principal technical authority across Custom Silicon (TPUs, gSOCs, ASICs) and off-the-shelf products (switches, PCIe, CXL, CPUs), evaluating vendor capabilities, architectural trade-offs, node roadmaps, and manufacturability.
Work with engineering to conduct technical evaluations of leading-edge and specialized process nodes, including sub-2nm, GAA/RibbonFET, and backside power delivery.
Partner with Tier-1 foundries to assess defect densities, DFM/PDK compliance, and process-window margins to secure optimal node execution.
Architect and qualify heterogeneous integration paths, including CoWoS, InFO, 3D stacking, and HBM integration.
Evaluate sub-tier components, including substrates and thermal-interface materials, and establish mechanical and thermal readiness gates such as mTV/eTV stress testing.
Drive technical evaluations across silicon architecture, manufacturing, and product engineering; establish technical should-cost foundations and define yield/test parameters to optimize total cost of ownership.
Partner with Platforms Engineering, Systems Architecture, and Cloud Supply Chain Operations on sourcing leverage, risk mitigation, and performance improvements.
Engage with foundries, merchant silicon vendors, advanced OSATs, and sub-tier material suppliers.