Lead silicon validation for optical chiplets, defining and driving the validation strategy from initial silicon power-on through block- and chip-level signoff. The role applies expertise in high-speed SerDes, photonic systems, and post-silicon validation to optical interconnect for next-generation AI infrastructure. The position covers validation of electronic-photonic SoCs, including bringup, functional validation, electrical characterization, and system-level testing. It includes first-silicon power-on for new tape-outs, hands-on post-silicon testing of SerDes interfaces, optical control loops, and mixed-signal blocks, and systematic investigation of silicon failure modes. The engineer establishes validation targets and signoff criteria using relevant industry standards and semiconductor best practices, provides technical leadership and mentorship to validation engineers, and maintains validation reports, signoff packages, and product performance documentation.
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Job Type
Full-time
Career Level
Principal