Principal Engineer, Silicon Validation

Ayar Labs•San Jose, CA

About The Position

Lead silicon validation for optical chiplets, defining and driving the validation strategy from initial silicon power-on through block- and chip-level signoff. The role applies expertise in high-speed SerDes, photonic systems, and post-silicon validation to optical interconnect for next-generation AI infrastructure. The position covers validation of electronic-photonic SoCs, including bringup, functional validation, electrical characterization, and system-level testing. It includes first-silicon power-on for new tape-outs, hands-on post-silicon testing of SerDes interfaces, optical control loops, and mixed-signal blocks, and systematic investigation of silicon failure modes. The engineer establishes validation targets and signoff criteria using relevant industry standards and semiconductor best practices, provides technical leadership and mentorship to validation engineers, and maintains validation reports, signoff packages, and product performance documentation.

Requirements

  • Bachelor's degree in Electrical Engineering or a related field and 10+ years of relevant industry experience, or a master's degree and 7+ years of experience.
  • Demonstrated leadership in post-silicon validation for complex SoCs or multi-chip packages, including first-silicon bringup and full signoff.
  • Hands-on expertise validating and characterizing high-speed SerDes, including NRZ and PAM-4, using equipment such as BERTs, oscilloscopes/DCAs, and network analyzers.
  • Strong proficiency in Python for laboratory automation, data analysis, and test infrastructure development.
  • Experience developing and owning validation test plans end-to-end.
  • Deep understanding of communication protocols and standards, including Ethernet and PCIe.
  • Excellent communication skills and ability to drive cross-functional technical alignment.

Nice To Haves

  • Familiarity with optical transceiver standards and co-packaged optics integration challenges.
  • Knowledge of high-speed standards including Ethernet (200G/400G/800G), PCIe Gen5/6, and OIF CEI.
  • Experience driving NPI and transitioning from laboratory validation to manufacturing test.

Responsibilities

  • Define and implement validation methodologies for electronic-photonic SoCs, covering initial bringup, functional validation, electrical characterization, and system-level testing.
  • Develop detailed test plans and success criteria, and select appropriate test equipment and methodologies.
  • Lead first-silicon power-on and bringup for new tape-outs, collaborating with firmware and design teams to establish operating conditions and validate core functionality.
  • Execute post-silicon validation of SerDes interfaces, optical control loops, and mixed-signal blocks using laboratory equipment.
  • Apply industry standards and semiconductor validation best practices to establish validation targets, coverage objectives, and signoff criteria.
  • Investigate silicon failure modes, including signal-integrity issues and mixed-signal anomalies, and drive them to closure with design and firmware teams.
  • Provide technical leadership and mentorship to senior and junior validation engineers, and guide the team's technical execution.
  • Create and maintain validation reports, signoff packages, and product performance documentation.
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