Principal Post-Silicon Validation Engineer

Astera Labs • San Jose, CA

7d

About The Position

Astera Labs is seeking a Principal Post-Silicon Validation Engineer to take connectivity silicon from first-silicon bring-up through production readiness. The role owns validation strategy for high-speed interconnect products, characterizes silicon in the lab, and leads root-cause analysis of challenging system-level issues. The work contributes to product quality, performance, and time-to-market for AI infrastructure connectivity products.

The engineer will architect and execute end-to-end post-silicon validation plans; lead silicon bring-up; debug and characterize silicon, firmware, and system behavior; build validation automation and lab infrastructure; analyze test data; and provide technical leadership. The role involves collaboration with design, architecture, product, DFT, customers, and Field Applications Engineers.

Requirements

• Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field.
• 8–12 years of experience in post-silicon validation, silicon bring-up, or hardware characterization.
• Hands-on experience with high-speed serial interfaces such as PCIe, including a strong understanding of the physical layer.
• Proficiency with lab equipment, including oscilloscopes, BERTs, protocol analyzers, and power supplies.
• Strong scripting and programming skills in Python and/or C/C++ for test automation.
• Proven ability to debug complex hardware and firmware issues to root cause.

Nice To Haves

• Master's degree or PhD in Electrical Engineering, Computer Engineering, or a related field.
• Experience with PCIe Gen 5 or Gen 6, Ethernet, or retimer products.
• Experience with SerDes characterization, equalization tuning, and link margining.
• Track record of taking multiple products from first silicon to volume production.
• Strong cross-functional communication skills and the ability to lead without direct authority.

Responsibilities

• Architect and drive end-to-end post-silicon validation plans, from first-silicon bring-up through characterization and production release.
• Define test strategies, coverage goals, and exit criteria in partnership with design, architecture, and product teams.
• Lead lab bring-up of new silicon, including board, firmware, and software readiness.
• Debug complex silicon, firmware, and system-level failures to root cause across the hardware/software boundary.
• Characterize high-speed serial link performance, including margining, signal integrity, and compliance, across process, voltage, and temperature.
• Partner with design and DFT teams to feed findings back into current and future product generations.
• Develop scalable validation automation frameworks and test content using Python and C/C++.
• Build and improve lab infrastructure, test benches, and data analysis flows to increase validation throughput.
• Analyze large validation datasets to identify trends, outliers, and risks early.
• Mentor engineers and establish validation methodology best practices across the team.
• Collaborate with customers and Field Applications Engineers to reproduce and resolve system-level issues.

Benefits

• The role may be eligible for discretionary bonus, incentives, and benefits.

What This Job Offers

• Job Type: Full-time
• Career Level: Principal