Principal Silicon Engineer
About The Position
Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) develops and operates the infrastructure and foundational technologies that support Microsoft’s online businesses and Azure platform. The Interface IP Team works on hardware manufacturing measures and processes, including planning, quality, delivery, scale, and sustainability. The team seeks an engineer to help develop customer-focused technical solutions for Microsoft’s cloud infrastructure. The Principal Silicon Engineer will own and drive microarchitecture and RTL design for complex silicon blocks and subsystems, translating architecture and system requirements into efficient, high-quality hardware. The role includes capturing and validating design intent for digital and mixed-signal blocks, providing static timing leadership for mixed-signal interfaces, and collaborating across design disciplines to meet timing, power, and functional requirements. The engineer will also contribute to design automation and flow improvements, including the use of AI, and communicate project status, risks, and mitigations to program leadership.
Requirements
- Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or a related field and 3+ years of technical engineering experience; or a master's degree in one of these fields and 6+ years of experience; or a bachelor's degree in one of these fields and 8+ years of experience; or equivalent experience.
- Ability to meet Microsoft, customer, and/or government security screening requirements, including the Microsoft Cloud Background Check upon hire or transfer and every two years thereafter.
- Ability to satisfy export-control eligibility requirements and provide citizenship or qualifying residency/protected-status documentation; citizenship will be verified with a valid passport, while lawful permanent residents, refugees, and asylees may verify their status.
Nice To Haves
- Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or a related field and 5+ years of technical engineering experience; or a master's degree in one of these fields and 8+ years of experience; or a bachelor's degree in one of these fields and 12+ years of experience; or equivalent experience.
- At least 1 year of experience working on or leading projects from beginning to end.
- At least 8 years of experience in RTL design and design checks, including CDC, RDC, VCLP, and LINT.
- At least 8 years of experience in synthesis, timing constraints, and PPA trade-offs.
- Proficiency in RTL-to-physical-design collateral development, including timing and synthesis constraints.
- Knowledge of the full RTL2GDS flow.
- Hands-on experience with industry tools for synthesis, STA, and physical design flows, such as PrimeTime, Genus/DC, and Innovus/ICC2.
- Proficiency in recent synthesis-tool capabilities and methods for QoR improvement.
- Proficiency in static timing analysis.
- Familiarity with RTL and gate-level power analysis and optimization, UPF, and power-intent verification.
- Proficiency in translating physical design results into feedback for flow or RTL improvement.
- Proficiency in Tcl and Python.
Responsibilities
- Own and drive microarchitecture and RTL design for complex silicon blocks and subsystems, translating architecture and system requirements into clean, efficient, high-quality hardware implementations.
- Lead the capture and validation of design intent for digital and mixed-signal blocks, ensuring accurate constraints and integration across front-end and physical design flows.
- Provide static timing leadership for mixed-signal interfaces, driving timing closure, exception quality, and correlation across MMMC corners.
- Partner with RTL, physical design, mixed-signal, DFT, and CAD teams to resolve cross-domain issues and maintain alignment on timing, power, and functional requirements.
- Contribute to design automation, including leveraging AI, constraint-checking, and flow improvements to improve execution efficiency and PPA.
- Operate with limited direction, demonstrate ownership and attention to detail, and communicate clear, data-driven status, risks, and mitigation plans to program leadership.
Benefits
- Certain roles may be eligible for benefits and other compensation; additional benefits and pay information is available through the linked Microsoft careers page.
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What This Job Offers
Job Type
Full-time
Career Level
Principal
