Principal Front-End Design Engineer
About The Position
Synopsys is a leader in silicon-to-systems engineering solutions, helping customers accelerate innovation in AI-driven products through EDA, IP, and design solutions. As a Principal Front-End Design Engineer, you will lead methodology, subsystem architecture, and AI-enabled design innovation across IP and SoC development. You will build scalable design solutions, improve engineering productivity, and drive best practices across global teams. You will join the Digital Methodology Interop Engineering team, which advances IP and subsystem design excellence and collaborates across global sites on methodology, tool integration, and best practices. The role is based in Sunnyvale, California and is not remote eligible. The role is an employee position. The base salary range across the U.S. is $191,000–$286,000. The position may also be eligible for an annual bonus, equity, and other discretionary bonuses. Synopsys offers health, wellness, and financial benefits; the recruiter can provide further details about the salary and benefits.
Requirements
- Bachelor’s or master’s degree in Electrical Engineering, Computer Engineering, or a related field.
- 10+ years of ASIC, SoC, or IP design and verification experience.
- Expertise in verification, synthesis, timing constraints, DFT, CDC/RDC, or lint methodologies.
- Strong experience with Synopsys tools such as VCS, VC SpyGlass, Fusion Compiler, Design Compiler, and TestMAX.
- Proficiency in SystemVerilog, UVM, Tcl, Python, or similar languages.
- Demonstrated technical leadership and influence across cross-functional engineering teams.
Nice To Haves
- Deep understanding of IP reuse, subsystem integration, and SoC development.
- Interest in applying AI to improve design productivity and quality.
- Strong problem-solving, communication, and mentoring skills.
- Ability to translate complex technical challenges into scalable, practical solutions.
Responsibilities
- Develop and deploy AI-driven solutions for verification, synthesis, constraints, and DFT workflows.
- Architect reusable subsystem reference designs for Synopsys IP.
- Debug and optimize front-end design methodologies and automation flows.
- Drive adoption of best practices across design and verification teams.
- Collaborate with EDA, IP, and customer-facing engineers to solve complex design challenges.
- Mentor engineers through technical leadership and knowledge sharing.
Benefits
- Comprehensive health, wellness, and financial benefits.
- May be eligible for an annual bonus, equity, and other discretionary bonuses.
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What This Job Offers
Job Type
Full-time
Career Level
Principal
