Principal Engineer, Physical Design (ASIC Place & Route) (San Jose, CA) (7429)

TSMC•San Jose, CA

65d•$140,000 - $220,000•Hybrid

About The Position

The Principal Physical Design Engineer leads end-to-end netlist-to-GDSII implementation for high-performance computing and AI silicon architectures, including complex, multi-million-gate blocks. The role drives block- and chip-level technical execution, defining and optimizing power, performance, and area (PPA) across advanced process nodes while addressing difficult physical and electrical design challenges. Based at TSMC Technology, Inc.’s San Jose Center of Excellence, the engineer works closely with customer partners and cross-functional architecture, CAD, and DFT teams. The position uses a hybrid collaboration model with four days on-site and requires regular on-site work, including at customer partner facilities across the South Bay Area.

Requirements

Master’s or Ph.D. degree in Electrical Engineering, Computer Engineering, Microelectronics, or a closely related technical field.
10+ years of hands-on full-chip or block-level physical design implementation and signoff experience, with a track record of successful tapeouts.
Mastery of industry-standard EDA tools, such as Synopsys Fusion Compiler/ICC2, PrimeTime, StarRC; Cadence Innovus, Tempus, Voltus; and Siemens Calibre.
Experience implementing designs in TSMC N16/N12 or below, with deep knowledge of advanced FinFET parasitic extraction, multi-patterning, and variability effects.
Proficiency in Tcl, Perl, and/or Python for building, maintaining, and debugging automation pipelines and signoff scripts.
Strong communication and cross-functional leadership skills.
Flexibility to work regularly on-site and at customer partner facilities across the South Bay Area.

Nice To Haves

Hands-on physical design and tapeout experience on advanced FinFET/GAA nodes, such as TSMC N5, N4, N3, or below.
Advanced expertise in low-power methodology, including multi-voltage domains, dynamic/static power gating (UPF/CPF), and retention strategies.
In-depth understanding of advanced timing signoff paradigms, including POCV, advanced OCV, and hyper-convergent signoff flows.
Demonstrated leadership of cross-functional task forces through critical tapeout milestones and complex foundry-interface debug cycles.

Responsibilities

Drive full-flow RTL/netlist-to-GDSII physical implementation for high-complexity blocks through synthesis, floorplanning, placement, clock tree synthesis, routing, and final signoff.
Create optimized floorplans, establish power delivery networks, and minimize congestion, channel utilization, and macro placement overhead.
Design low-skew, variation-aware clock tree architectures to maximize frequency margins within power budgets.
Perform timing closure and post-route optimization, including functional and timing engineering change orders across multi-corner, multi-mode scenarios.
Lead analyses of signal electromigration, dynamic cross-talk noise, and power rail integrity (IR drop) to meet reliability targets.
Direct physical verification signoff by debugging and resolving DRC, LVS, ERC, and antenna violations in alignment with foundry design rule manuals.
Develop automation frameworks and methodology enhancements using Tcl and Python and/or Perl to improve tapeout velocity and PPA predictability.
Collaborate with architecture, CAD, DFT, and customer partner teams on physical design execution and methodology.
Lead cross-functional task forces through tapeout milestones and foundry-interface debug cycles (preferred qualification).