Principal Digital Verification Engineer

Ciena Government Solutions•Rochester, NY

2d•Onsite

About The Position

As the global leader in high-speed connectivity, Ciena builds the critical infrastructure powering the AI era. We’re a technology company shaping the future of networking, guided by innovation, integrity, and collaboration. Through development opportunities, meaningful work, and flexibility, Ciena supports growth and well-being—on and off the job. Connect with a career that matters. How You Will Contribute: The Wavelogic family of products is widely used in Ciena's optical fiber transmission solutions and is one of the main contributors to Ciena's success in the telecommunications industry. To further strengthen our team, we are looking for an expert digital verification engineer who will be involved in the verification of these products, working within a team of digital design engineers, verification engineers and architects, in our Rochester NY office. Your role as an expert digital verification engineer will be to propose and implement innovative verification strategies, in order to thoroughly simulate and validate functional blocks, cores, and subsystems for the Wavelogic family of products.

Requirements

Minimum Bachelor’s degree in Electrical or Computer Engineering, Computer Science or other applicable scientific degree coupled with expert level experience in the use of System Verilog, UVM, SVA, and simulators from major vendors.
Proven ability in determining appropriate and comprehensive digital verification and coverage strategies.
Highly motivated self-starter, able to work independently, while being a great teammate.
Ability to methodically address (debug) sophisticated technical problems.
Excellent organization, written and oral English communication skills.

Nice To Haves

Experience with Formal verification methods
DSP and/or Forward Error Correction
Using Jira for bug tracking and GIT for source code management and revision tracking
Familiarity with programming languages such as: Python, Make, bash, object-oriented programming, C, C++.

Responsibilities

Understand the architecture and functional requirements of the project to effectively communicate and collaborate with systems engineers and architects.
Responsible for the complete and detailed validation of entire subsystems by using an appropriate combination of simulation, formal and coverage methods.
Responsible for creating, reviewing and optimizing simulation environment components, test case scenarios as well as functional coverage and formal verification test plans.
Lead focused groups of individuals or mentor individuals and manage their priorities towards reaching a specific set of objectives.
Accountable for estimating schedules, tracking them towards timely completion, and providing clear and precise status updates at regular intervals.
As an ASIC Verification Prime, be responsible for all aspects of the verification of the digital portion of the Serdes as well as working with partner teams to ensure overall Serdes coverage.
Participate in architectural and design reviews to proactively advise on verification impacts and improvements for schedule and or coverage.