Principal Design Verification Engineer (AI Fabric Switches)

Astera Labs • San Jose, CA

20h • $185,000 - $240,000

About The Position

Astera Labs is seeking a Principal Design Verification Engineer to contribute to functional verification of complex ASICs, including AI fabric switches. The role covers the full verification lifecycle, from planning and test development through debugging and coverage collection and closure. The engineer will develop verification approaches that may combine directed and constrained-random techniques, and will work with software and system validation teams to develop test plans and execute them on emulation platforms. The position also involves collaborating with RTL designers to debug failures and helping ensure high-quality tape-out.

Requirements

• Bachelor’s degree in Electrical Engineering or higher; a Master’s degree is preferred.
• At least 8 years of experience verifying and validating complex SoCs for server, storage, and networking applications.
• Experience with the full verification lifecycle using SystemVerilog, UVM, C, and/or C++.
• Proven ability to combine and deploy directed and constrained-random verification techniques.
• Experience with bug and coverage hunting.
• Knowledge of industry-standard simulators, revision control systems, and regression systems.
• Ability to develop test plans and test sequences independently and collaborate with RTL designers to debug failures.
• Ability to identify and write coverage measures for stimulus and corner cases and close coverage to identify verification gaps.
• Professional attitude, ability to prioritize multiple changing tasks, and ability to work with minimal guidance and supervision.
• Entrepreneurial, open-minded, customer-minded, can-do approach, with ability to think and act quickly.
• Authorized to work in the United States and able to start immediately.

Nice To Haves

• Master’s degree in Electrical Engineering.
• Experience with formal methods.
• Experience using Perl or Python scripting to automate verification infrastructure.
• Experience using third-party Verification IP for protocols such as PCI Express Gen 3 or later, Ethernet, InfiniBand, DDR4/5, NVMe, or USB.
• Experience with directed-test methodologies, cache verification, and formal methods.
• Experience with SystemVerilog, C, C++, Python, or other scripting languages.

Responsibilities

• Plan and carry out the full verification lifecycle, including test planning, test writing, debugging, and coverage collection and closure.
• Develop test plans and sequences to generate stimulus, working independently and collaborating with RTL designers to debug failures.
• Apply hybrid verification techniques, including directed and constrained-random testing.
• Identify and implement coverage measures for stimulus and corner cases, then close coverage to find verification holes.
• Work with software and system validation teams to develop test plans and execute them on emulation platforms.
• Use coding and problem-solving skills to contribute to functional verification of designs.

What This Job Offers

• Job Type: Full-time
• Career Level: Principal