Principal Competitive CPU Microarchitecture & Platform Performance Engineer

Advanced Micro Devices, Inc•UNAVAILABLE, Texas

4d•Hybrid

About The Position

At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future. Whether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger — technology that moves the world forward. Join us and, together, we’ll advance your career. The Competitive Advanced Performance (CAP) team is a new, visible capability focused on predicting, validating and explaining competitive server CPU performance before products reach the market. Joining now means helping define the methods, tools and operating model from the ground up. AMD is looking for an engineer who can build workload-relevant models of future AMD and competitor server platforms before silicon is available. You will convert public disclosures, measured behavior, partner-authorized data and software or platform observations into explicit assumptions about future Intel, Arm, hyperscaler custom, NVIDIA, Qualcomm and emerging CPU designs. This is not a static feature-comparison role; the work must explain what a platform is likely to deliver on real workloads, why, and with what level of confidence. You enjoy proving architectural models against real workloads. You can reason from incomplete information without hiding uncertainty, connect microarchitectural mechanisms to observed bottlenecks, and communicate the result in a way that is useful to both deep technical experts and senior decision-makers. You are equally comfortable with performance counters, analytical models, diagrams and written argument.

Requirements

Deep hands-on experience in CPU microarchitecture, silicon performance, system architecture or performance modeling.
Strong knowledge of out-of-order pipelines, branch prediction, fetch and decode, execution back ends and simultaneous multithreading behavior.
Expertise in cache, TLB, coherence, prefetching, memory controllers, NUMA, bandwidth, latency and capacity scaling.
Experience with hardware performance counters, profiling tools, microbenchmarks, system telemetry and bottleneck analysis.
Strong quantitative and scripting or data-analysis skills used in performance investigations.
Ability to reason from incomplete information, make assumptions explicit and show which unknowns can change the conclusion.
Clear technical writing and visualization skills, with a commitment to configuration control, peer review and reproducibility.

Nice To Haves

Pre-silicon performance modeling, architecture exploration or simulation experience.
Hands-on analysis of more than one server CPU architecture or ISA.
Experience with memory-intensive workloads, virtualization, HPC, analytics or CPU-side AI workloads.
Familiarity with power modeling, thermals, platform firmware and frequency or power-management behavior.
Experience evaluating vendor disclosures, patents, conference presentations or public technical materials under clean-room rules.

Responsibilities

Develop comparative models of CPU front ends, execution resources, branch behavior, cache and TLB hierarchies, coherence, memory subsystems and multi-socket or NUMA behavior.
Model platform constraints and advantages including memory bandwidth and capacity, DDR or HBM attachment where relevant, PCIe, CXL, networking, storage paths, power limits and thermals.
Translate incomplete roadmap disclosures into explicit assumptions with confidence levels, alternate cases and sensitivity ranges.
Use measured silicon, performance counters and platform telemetry to calibrate models and identify failing assumptions.
Perform bottleneck decomposition that explains why a workload favors AMD or a competitor and which architectural mechanism is responsible.
Work with workload engineers to create microbenchmarks and kernels that isolate high-value architectural effects.
Evaluate ISA and acceleration features in the context of real application uplift rather than theoretical peak capability.
Quantify performance-per-watt, platform power and rack-density implications when architectural choices change system behavior.
Maintain version-controlled assumptions, sources, revisions and uncertainty so forecasts can be peer reviewed and reproduced.
Create architecture diagrams, technical narratives and executive-ready content that clearly show causes, risks and areas of AMD advantage.