Engineer, CPU Performance Verification

Tenstorrent•Austin, TX

4h•$100,000 - $500,000•Hybrid

About The Position

Tenstorrent is seeking an engineer to join its CPU design team and drive performance verification and correlation between RTL and the performance model for a CPU based on the RISC-V ISA. The role collaborates with core architects and RTL teams to deliver an efficient, high-performance design. The position is hybrid and based in Austin, Texas, or Santa Clara, California. Candidates at various experience levels are welcome; the appropriate level will be assessed during interviews, and the offer will align with that level, which may differ from the posting. The role focuses on verifying CPU performance, correlating RTL against the performance model, identifying and debugging performance bottlenecks and miscorrelation, and improving performance analysis tools and methodologies. It includes drafting performance test plans, developing targeted microbenchmarks, and conducting experiments to evaluate power, performance, and area. Tenstorrent describes its team as collaborative, curious, and committed to solving difficult technical problems. The role offers exposure to CPU design from microarchitecture through performance convergence and validation, as well as pre-silicon and post-silicon optimization and performance modeling, simulation, and emulation flows. Compensation for engineers ranges from $100,000 to $500,000, including base and variable compensation targets; actual offers depend on experience, skills, education, background, and location. Employment is contingent on eligibility to access U.S. export-controlled technology, which may depend on citizenship or permanent residency status or obtaining required license approval.

Requirements

Experience analyzing modern CPU performance data, identifying bottlenecks, and building tools to analyze them efficiently.
Skill in C++ and Python.
Understanding of industry-standard tools for compilation, simulation, and emulation.
Knowledge of the architecture and microarchitecture of high-performance CPU cores.
Proficiency debugging RTL or logic across multiple design hierarchies and pre-silicon environments.
Exposure to performance modeling and RTL-to-model correlation.
Ability to identify problems and develop solutions.

Responsibilities

Drive performance verification and correlate RTL with the performance model.
Collaborate with RTL engineers and core architects to meet performance goals.
Debug miscorrelation and verify performance features.
Draft performance test plans and develop targeted microbenchmarks to exercise performance features and expose bottlenecks.
Enhance tools and methodologies for performance analysis and correlation to improve development efficiency.
Conduct performance experiments, evaluate results, and use techniques to optimize power, performance, and area.
Analyze CPU performance data, identify bottlenecks, and build tools to support efficient analysis.