CPU Performance Architect

Google•Mountain View, CA

5h•$163,000 - $236,000

About The Position

Join a team developing custom silicon solutions for Google's direct-to-consumer products. The role contributes to the next generation of hardware experiences, focusing on performance, efficiency, and integration. The team combines AI, software, and hardware to create new technologies and computing experiences. Individual pay is determined by job-related skills, experience, and relevant education or training. US compensation is $163,000–$236,000, plus a 15% bonus target, equity, and benefits.

Requirements

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
8 years of experience with performance analysis, microarchitectural bottleneck isolation, and workload characterization.
Experience with C/C++ for architectural modeling and Python for data analysis and automation frameworks.

Nice To Haves

Master's degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science, with an emphasis on computer architecture.
Experience with the ARM instruction set architecture (ISA) and ecosystem.
Experience characterizing and optimizing mobile or client platform power/performance and thermal management states, such as DVFS.
Understanding of low-level system software components, including the Linux kernel, device drivers, power management frameworks, and runtimes.

Responsibilities

Lead in-depth microarchitectural analysis on silicon to isolate and quantify pipeline stalls, memory hierarchy bottlenecks, and instruction-level inefficiencies, and drive root-cause resolution.
Design, build, and execute power and performance experiments on physical silicon, correlating pre-silicon projections with post-silicon results across general-purpose and AI/ML workloads.
Develop and maintain early-stage power and performance models to evaluate architectural scenarios and drive hardware-software co-optimization.
Partner with lead CPU architects and cross-functional teams to define dynamic, realistic power and performance goals for future Google silicon.