Lead CPU Performance Architect

Google•Austin, TX

23h•$192,000 - $278,000

About The Position

Be part of a team developing custom silicon solutions for Google's direct-to-consumer products. The team combines Google AI, Software, and Hardware to research, design, and develop technologies and hardware that make computing faster, seamless, and more powerful. In this role, you will help shape future hardware experiences by delivering performance, efficiency, and integration through CPU microarchitecture work. Individual pay is determined by job-related skills, experience, and relevant education or training. The listed US compensation is $192,000–$278,000 USD, plus a 20% bonus target, equity, and benefits.

Requirements

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
10 years of experience with CPU microarchitecture design and performance modeling.
Experience with software performance analysis and improvement, and high-performance computer architectures such as CPU, memory subsystem, and multiprocessing.
Experience in performance modeling, performance analysis, workload characterization, or PPA optimization.
Experience in C/C++ or other scripting languages.

Nice To Haves

PhD degree in Electrical Engineering, Computer Engineering, or Computer Science with a focus on computer architecture.
Experience leading CPU microarchitectural exploration, defining specifications, and building high-fidelity C/C++ performance models.
Experience with modern processor instruction set architectures (ISAs) such as ARM, RISC-V, or x86.
Experience with system software stacks, including operating system kernels (Linux), device drivers, and runtime environments.
Experience guiding technical strategy and mentoring engineers.
Ability to communicate fluently in English to support client relationship management in this region.

Responsibilities

Develop innovative microarchitectural features to significantly enhance CPU performance.
Model complex core microarchitectural concepts and evaluate Performance, Power, and Area (PPA) trade-offs to deliver a buildable, production-ready microarchitecture.
Define and document comprehensive CPU subsystem microarchitecture specifications.
Lead cross-functional collaboration with RTL, physical design, and verification teams to ensure a high-performance, power-efficient CPU implementation.
Drive performance correlation between the performance model and RTL implementation, and perform pre-silicon and post-silicon performance bug triage.