Pre-Silicon Digital Verification Engineer

Apple • Sunnyvale, CA

2h

About The Position

Apple is seeking a Pre-Silicon Digital Verification Engineer to verify complex digital IP for mixed-signal integrated circuits used in current and future Apple products. The role is part of a mixed-signal ASIC team and involves working with system architects and digital designers to make block-level specifications clear and precise, then using those specifications to plan and perform verification. The engineer will create verification testbenches using formal verification and UVM-based simulation, and develop SystemVerilog Assertions and constrained-random UVM testcases to achieve functional and code coverage. The position also offers opportunities to work with formal verification, digital mixed-signal verification, and analog mixed-signal simulation tools. The team supplies silicon to Apple hardware development teams and provides mentorship to engineers entering mixed-signal ASIC development.

Requirements

• A minimum of a bachelor's degree in a related field.

Nice To Haves

• Extensive coursework in digital design and computer architecture.
• A foundation in object-oriented programming techniques.
• Lab courses or work experience with SystemVerilog.
• Familiarity with constrained-random verification techniques.
• Familiarity with clock domain crossing design and verification techniques.
• Some coursework in analog circuit design.

Responsibilities

• Collaborate in developing precise design specifications for digital control blocks.
• Use design specifications to create block- and chip-level verification plans.
• Architect and create block-level verification elements.
• Assist in architecting chip- and system-level verification environments.
• Use SystemVerilog and UVM to develop drivers, tests, reference models, and checkers.
• Debug test failures and work with designers to develop fixes.
• Use functional and code coverage to track progress and gauge tapeout readiness.
• Create verification testbenches using formal verification and UVM-based simulation.
• Develop SystemVerilog Assertions and constrained-random UVM testcases.
• Participate in code reviews of other chip blocks and propose efficient verification approaches.

What This Job Offers

• Job Type: Full-time