Pre-Silicon Digital Verification Engineer
About The Position
Apple is seeking a Pre-Silicon Digital Verification Engineer to join its mixed-signal ASIC team, which develops custom integrated circuits for existing and future Apple product lines. The engineer will verify complex digital IP and collaborate with system architects and digital designers to define clear, precise block specifications and create verification plans covering functional behavior, performance, stress cases, and error conditions. The role owns the creation of verification testbenches using formal verification and UVM-based simulation. It involves developing SystemVerilog Assertions and constrained-random UVM test cases to achieve functional and code coverage, debugging test failures with designers, and participating in reviews of other chip blocks. The engineer may also work with digital mixed-signal verification and analog mixed-signal simulation using state-of-the-art tools. The team is described as small, close-knit, high-performing, and ready to mentor engineers entering mixed-signal ASIC development.
Requirements
- Bachelor of Science degree.
- A minimum of 3 years of relevant industry experience.
Nice To Haves
- Extensive coursework in digital design and computer architecture.
- A foundation in object-oriented programming techniques.
- Lab courses or work experience with SystemVerilog.
- Familiarity with constrained-random verification techniques.
- Familiarity with clock-domain-crossing design and verification techniques.
- Some coursework in analog circuit design.
Responsibilities
- Collaborate in developing precise design specifications for digital control blocks.
- Use design specifications to create block- and chip-level verification plans.
- Architect and create block-level verification elements.
- Assist in architecting chip- and system-level verification environments.
- Use SystemVerilog and UVM to develop drivers, tests, reference models, and checkers.
- Debug test failures and work with designers to develop fixes.
- Use functional and code coverage to track progress and gauge tapeout readiness.
- Create verification testbenches using formal verification and UVM-based simulation.
- Develop SystemVerilog Assertions and constrained-random UVM test cases.
- Participate in code reviews of other blocks and propose ways to achieve bug-free designs on the first tapeout.
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What This Job Offers
Job Type
Full-time
Career Level
Mid Level
