Digital Verification Engineer

Efficient Computer • Austin, PA

1d

About The Position

Efficient Computer is seeking a Design Verification Engineer to join its newly formed verification team and own functional verification of blocks and subsystems in its SoC, including the proprietary Fabric technology. The engineer will work with senior design verification engineers, RTL designers, and architects to develop testbenches, close coverage, and identify bugs before silicon. The position offers the opportunity to influence products and verification processes as the company progresses from initial product development to market release and scaled volume production.

Requirements

• Bachelor's or Master's/PhD degree in Electrical Engineering, Computer Engineering, or a related field.
• At least 4 years of ASIC/SoC design verification experience, with multiple projects taken through tapeout.
• Hands-on experience building and extending UVM testbench components, including agents, scoreboards, and sequences, and developing constrained-random tests.
• Experience defining functional coverage and driving code and functional coverage closure at block or subsystem level.
• Working knowledge of SystemVerilog Assertions.
• Ability to independently debug simulation failures using waveforms, logs, and design knowledge.
• Proficiency in Python for test automation, log analysis, and regression flows.
• Ability to clearly report verification status and issues to the team.

Nice To Haves

• C/C++ experience for reference models or DPI-based verification.
• Exposure to formal verification tools such as JasperGold or similar.
• Experience building or using AI agentic flows for design verification.
• Knowledge of computer architecture or dataflow architectures.
• Exposure to power-aware verification (UPF).

Responsibilities

• Develop and maintain UVM/SystemVerilog testbenches, sequences, and tests for block- and subsystem-level verification.
• Write verification plans from design specifications in collaboration with design and architecture teams.
• Write SystemVerilog assertions and functional coverage models, and drive coverage to closure.
• Debug simulation failures with designers to identify root causes and fix issues.
• Contribute to regression infrastructure, automation, and dashboards that track verification progress.
• Support gate-level simulation and other sign-off activities.

Benefits

• Competitive base salary generally ranging from $130,000 to $180,000.
• 10% annual bonus.
• Meaningful equity.
• Comprehensive benefits.
• 401(k) match.
• Company-paid benefits.
• Paid parental leave.
• Flexibility.
• Opportunities to grow skills and career.

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level