Senior Digital Verification Engineer - Contract

Efficient Computer•Austin, TX

1d•$80 - $130

About The Position

Efficient Computer is seeking a Senior Digital Verification contractor to take ownership of verification for complex blocks and subsystems in their SoC, including Efficient's proprietary Fabric technology. The role involves joining a newly formed Verification & Emulation team and working directly with RTL designers and architects. The ideal candidate will be able to quickly understand specifications, set up or extend UVM environments with minimal guidance, and drive verification to coverage closure.

Requirements

Bachelor's or Master's/PhD in Electrical Engineering, Computer Engineering, or a related field.
8+ years of ASIC/SoC design verification, with multiple projects taken from testbench development through tapeout.
Expert in UVM testbench architecture and SystemVerilog for verification, including classes, constraints, interfaces, functional coverage, and assertions (SVA).
A track record of driving functional and code coverage to sign-off on multi-million-gate designs.
Strong ability to debug complex simulation failures independently using industry-standard tools (VCS/Verdi, Xcelium, or Questa).
Python for regression automation, log analysis, and coverage post-processing.
Able to ramp quickly on a new design and deliver with minimal supervision.
Clear written and verbal communication of status, risks, and tradeoffs to peers and leadership.

Nice To Haves

C/C++ for reference modeling or SoC-level tests, including DPI integration.
Formal verification with JasperGold or similar tools.
Experience building or using agentic AI flows for DV, such as automated regression triage or failure debug.
Background in computer architecture, dataflow or spatial architectures, or ML accelerators.
Power-aware verification with UPF.

Responsibilities

Own verification of assigned blocks and subsystems from spec review through coverage sign-off.
Write verification plans from design and architecture specifications, and review them with design and architecture leads.
Architect, build, or extend UVM/SystemVerilog testbenches: agents, scoreboards, reference models, sequences, and constrained-random tests.
Write SystemVerilog assertions and functional coverage models, and drive functional and code coverage to closure.
Debug complex simulation failures and work with RTL designers to root-cause and fix bugs.
Report verification status, risks, and coverage gaps clearly to the DV lead and design team.
Document your environment so it can be handed off to and maintained by the full-time team.