Senior Engineer, Digital Verification

Analog Devices•Durham, NC

7d•Onsite

About The Position

As a Senior Analog/Mixed-Signal (AMS) Design Verification Engineer at Analog Devices, you will own verification planning and execution for complex mixed-signal integrated circuits and subsystems. You will translate specifications into scalable verification architectures, develop reusable SystemVerilog/UVM and real-number modeling solutions, and drive coverage closure across digital, analog, and mixed-signal interfaces. Working independently with minimal supervision, you will partner with analog, digital, modeling, firmware, and validation teams to identify risk early, resolve complex failures, and deliver robust products from pre-silicon verification through silicon bring-up.

Requirements

Advanced proficiency building reusable agents, sequences, scoreboards, reference models, assertions, and coverage components for block-, subsystem-, and SoC-level verification.
Strong understanding of analog circuits and specifications, including sampling, quantization, noise, offset, gain, settling, linearity, clocking, feedback, calibration, and process-voltage-temperature effects.
Hands-on experience with real-number modeling and behavioral model development using SystemVerilog real/wreal, Verilog-AMS, Verilog-A, or comparable abstraction techniques.
Experience configuring and debugging analog, digital, and mixed-signal simulations using industry-standard simulators and understanding accuracy-versus-performance tradeoffs.
Proven ability to convert specifications into executable verification plans and achieve requirements, functional, assertion, and code coverage closure.
Expertise in constrained-random, coverage-driven, assertion-based, and directed verification, including negative testing and corner-case analysis.
Working knowledge of power-state transitions, reset and startup sequences, clock and power-domain crossings, low-power intent, and verification of UPF-defined behavior.
Strong Python proficiency and working knowledge of Tcl, Perl, shell, or similar languages for regressions, data analysis, failure triage, and flow automation.
Demonstrated ability to diagnose complex cross-domain failures using simulation waveforms, logs, assertions, coverage reports, and quantitative data analysis.
Familiarity with common control and data interfaces such as SPI, I²C, APB, AHB, AXI, and high-speed serial or converter data paths, as applicable.
Ability to explain verification risk and results clearly, lead technical reviews, mentor peers, and influence cross-functional execution.

Nice To Haves

Master’s degree is preferred.
Typically 4–8 years of relevant IC verification experience, including substantial ownership of analog/mixed-signal verification environments or complex mixed-signal features.
Demonstrated experience carrying verification from planning and environment development through coverage closure, sign-off, and post-silicon correlation.
Experience with data converters, power management, clocking, sensor interfaces, RF/mixed-signal signal chains, or precision analog products is preferred.

Responsibilities

Own feature-based verification plans, requirements traceability, risk assessment, test strategy, and sign-off criteria for complex AMS IP, subsystems, and SoCs.
Architect scalable, reusable verification environments that combine SystemVerilog/UVM, analog behavioral models, real-number models, and mixed-signal simulation.
Develop and validate behavioral models in SystemVerilog real-number modeling, Verilog-AMS, or equivalent languages to accelerate full-chip verification while maintaining model fidelity.
Create constrained-random and directed tests, scoreboards, reference models, assertions, monitors, and functional coverage for analog-digital interactions, control loops, power modes, calibration, and fault conditions.
Define measurable code, functional, assertion, and requirements coverage goals; analyze gaps; drive closure; and communicate verification readiness and residual risk.
Lead cross-domain debug using waveforms, logs, assertions, schematics, and analog measurements to isolate failures involving timing, power sequencing, connectivity, modeling, and design behavior.
Build reliable regression flows, triage infrastructure, dashboards, and automation that improve simulation throughput, reproducibility, and engineering productivity.
Collaborate closely with analog and digital designers, architects, firmware engineers, model developers, and post-silicon validation teams throughout the product lifecycle.
Mentor engineers, lead reviews, establish verification best practices, and influence methodology, tool, and reuse decisions across projects.