Senior Verification Engineer

AccelerComm•,

8d•Hybrid

About The Position

The Senior Verification Engineer will support complete UVM verification of Accelercomm IP. The role is part of the RTL team, which delivers efficient ASIC and FPGA implementations of advanced communications algorithms across IP development, integration, and verification. The engineer verifies RTL implementations for advanced wireless communications IP and modem subsystems, ensuring they meet functional, performance, and quality requirements before FPGA deployment and ASIC tape-out. The role also includes supporting integration, automation, verification sign-off, and junior colleagues.

Requirements

Degree in Electronic Engineering, Computer Engineering, or a related discipline.
At least 3 years of experience verifying digital ASIC and/or FPGA designs.
Strong SystemVerilog and UVM skills.
Understanding of RTL design principles and hardware implementation.
Experience with coverage-driven and assertion-based verification.
Linux proficiency and scripting skills in Python, Tcl, or Bash.
Strong analytical, debugging, and problem-solving skills.
Experience using AI to accelerate verification without sacrificing quality.
Ability to work across multiple teams.

Nice To Haves

Experience in 4G/5G, NTN, satellite communications, or DSP systems.
Knowledge of modem architectures and Layer 1 processing.
Experience with Formal Verification, FPGA prototyping, and CI environments.
Familiarity with MATLAB or equivalent modelling tools.

Responsibilities

Verify RTL implementations for advanced wireless communications IP and modem subsystems against functional, performance, and quality requirements.
Develop verification plans from design and architecture specifications.
Create and maintain SystemVerilog/UVM verification environments.
Develop testbenches, assertions, scoreboards, and coverage models.
Execute directed and constrained-random verification.
Analyse coverage and debug RTL and verification issues.
Support subsystem and system-level integration activities.
Contribute to automation, regression, and CI workflows.
Participate in design reviews and verification sign-off.
Mentor and support junior colleagues.