Senior Digital Verification Engineer - Contract

Efficient Computer•Austin, PA

About The Position

Efficient Computer is hiring a senior Digital Verification contractor to own verification for complex blocks and subsystems in its SoC, including the company's proprietary Fabric technology. The role is part of the newly formed Verification & Emulation team and involves working directly with RTL designers and architects. The contractor is expected to ramp quickly on specifications, build or extend UVM environments with minimal direction, and drive verification through coverage closure and sign-off. The role is offered on a 1099 contract basis at a competitive hourly rate of $80–$130, with final compensation dependent on experience, seniority, and location. Efficient Computer is developing its Fabric architecture to improve energy efficiency for general-purpose computing, including AI. Its first processor, Electron E1, is shipping in volume, and the company is scaling its architecture toward data center performance. The company describes its work as building hardware and software for applications including autonomous machines, intelligent infrastructure, wearables, and space systems.

Requirements

Bachelor's, Master's, or PhD in Electrical Engineering, Computer Engineering, or a related field.
At least 8 years of ASIC/SoC design verification experience, with multiple projects taken from testbench development through tapeout.
Expertise in UVM testbench architecture and SystemVerilog verification, including classes, constraints, interfaces, functional coverage, and assertions (SVA).
Track record of driving functional and code coverage to sign-off on multi-million-gate designs.
Ability to independently debug complex simulation failures using industry-standard tools such as VCS/Verdi, Xcelium, or Questa.
Python skills for regression automation, log analysis, and coverage post-processing.
Ability to ramp quickly on a new design and deliver with minimal supervision.
Clear written and verbal communication of status, risks, and tradeoffs to peers and leadership.

Nice To Haves

C/C++ experience for reference modeling or SoC-level tests, including DPI integration.
Formal verification experience with JasperGold or similar tools.
Experience building or using agentic AI flows for design verification, such as automated regression triage or failure debugging.
Background in computer architecture, dataflow or spatial architectures, or ML accelerators.
Power-aware verification experience with UPF.

Responsibilities

Own verification of assigned blocks and subsystems from specification review through coverage sign-off.
Write verification plans based on design and architecture specifications, and review them with design and architecture leads.
Architect, build, or extend UVM/SystemVerilog testbenches, including agents, scoreboards, reference models, sequences, and constrained-random tests.
Write SystemVerilog assertions and functional coverage models, and drive functional and code coverage to closure.
Debug complex simulation failures and collaborate with RTL designers to identify root causes and fix bugs.
Clearly report verification status, risks, and coverage gaps to the DV lead and design team.
Document the verification environment so it can be handed off to and maintained by the full-time team.