Design Verification Engineer, Silicon
Meta•Austin, TX
•$146,000 - $209,000
About The Position
Meta Reality Labs is building custom silicon for next-generation augmented and virtual reality devices, including headsets and wearables. The Design Verification Engineer will ensure the functional correctness and quality of complex custom chips that enable immersive AR/VR experiences. The role develops and executes verification strategies for digital logic blocks and subsystems, collaborating with design, architecture, and software teams to bring high-performance, low-power silicon from specification to tape-out.
Requirements
- Bachelor's degree in Computer Science, Computer Engineering, a relevant technical field, or equivalent practical experience.
- At least 6 years of experience in digital design verification, including developing UVM-based constrained-random testbenches for RTL blocks, subsystems, or SoCs.
- At least 6 years of experience with hardware description and verification languages, including SystemVerilog and/or VHDL.
- Experience defining and closing functional coverage models and code coverage metrics for complex digital designs.
- Experience debugging RTL simulations using waveform analysis tools and log-based root-cause analysis.
- Experience with scripting languages such as Python or Perl for test automation, regression management, or coverage analysis.
Nice To Haves
- Experience with hardware/software interoperability verification and firmware validation.
- Experience with post-silicon validation, hardware bring-up, or transitioning pre-silicon test content to physical hardware.
- Experience verifying silicon for mobile, wearable, or consumer electronics SoCs, including low-power design verification techniques and performance.
- Familiarity with formal verification tools and methodologies.
- Familiarity with agentic AI flows.
- Experience with CPUs, AI accelerators, security, interconnect, and memory controllers.
- Experience with full SoC verification and bare-metal-based frameworks.
Responsibilities
- Develop and own verification plans for digital logic blocks, subsystems, or SoCs in custom AR/VR and AI silicon, covering functional coverage, corner cases, and compliance requirements.
- Design and implement constrained-random UVM testbenches for complex RTL designs, including processors, interconnects, memory controllers, multimedia accelerators, AI accelerators, and full SoCs.
- Define and close functional coverage models and code coverage metrics to ensure thorough verification of design intent.
- Collaborate with cross-functional teams to define verification plans and close coverage.
- Develop and maintain simulation infrastructure, regression frameworks, and automated test frameworks to support continuous integration of design changes.
- Perform formal verification and property checking on critical design blocks to complement simulation-based verification.
- Debug failing simulations and regressions by analyzing waveforms, log files, and RTL code to identify root causes in designs or testbenches.
- Partner with post-silicon validation and firmware teams to develop pre-silicon test content that transitions to hardware bring-up.
- Contribute to verification methodology improvements, including reusable verification collateral and shared infrastructure across the silicon team.
- Track and report verification progress, coverage closure status, and risk areas to design and program management stakeholders.
Benefits
- Bonus
- Equity
- Benefits
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What This Job Offers
Job Type
Full-time
Career Level
Senior
