Pre-Silicon Verification Engineer

Intel Corporation•Austin, TX

2d•$122,440 - $172,860•Hybrid

About The Position

About Intel's Central Engineering Group Intel's Central Engineering Group (CEG) focuses on enhancing engineering execution and expanding market opportunities through internal product development and external ASIC design services. Guided by a data-driven approach, CEG drives scalable, impactful solutions across Intel's engineering processes while maintaining a commitment to delivering high-quality results. Join a team dedicated to revolutionizing engineering methodologies and supporting Intel's industry leadership. Position Overview As an IP Design Verification Engineer, you will play a crucial role in ensuring the functional accuracy and reliability of clock generator IPs, such as PLL and FLL, within Intel's innovative product development lifecycle. You will actively develop verification environments, implement tests, and debug pre-silicon issues to meet rigorous specification requirements. Your contributions will directly impact the seamless integration of IPs into Intel's cutting-edge designs and ensure the highest standards of quality and performance.

Requirements

A collaborative mindset with the ability to work effectively across cross-functional teams including architects, RTL developers, and analog design teams
Strong attention to detail when documenting test plans, debugging pre-silicon issues, and ensuring conformance to specification requirements
A proactive approach to problem-solving, with the ability to root-cause complex technical issues and drive them to resolution
Bachelor's Degree in Electrical or Computer Engineering or a related field, with 4+ years of relevant experience; OR Master's Degree in Electrical or Computer Engineering or a related field, with 3+ years of relevant experience; OR PhD in Electrical or Computer Engineering or a related field, with 1+ years of relevant experience
2+ years of experience in/with: Design verification and validation methodologies, including UVM, System Verilog, and industry-standard EDA tools
2+ years of experience in/with: Scripting languages such as Python and Perl

Nice To Haves

Expertise in System Verilog UVM coding and debugging
Familiarity with PLL/FLL or SOC clocking and related RTL development

Responsibilities

Develop test benches, verification environments, and tests using System Verilog and UVM to ensure comprehensive IP validation
Perform functional verification for clock generator IPs such as PLL and FLL, ensuring conformance to microarchitecture specifications
Maintain and refine verification infrastructure and methodologies for multiple IP generations
Debug and root-cause pre-silicon issues within the verification environment
Document test plans and participate in technical reviews with design teams
Collaborate cross-functionally with architects, RTL developers, and analog design teams to enhance verification of architectural and microarchitectural features
Lead Mixed Signal Validation activities, including AMS simulations, schematic debugging, and resolving cross-functional issues
Contribute to the definition and refinement of architectural and microarchitectural features for IP design