Physical Design Engineer II

Microsoft • Redmond, WA

4d

About The Position

Microsoft Silicon, Cloud, Hardware, and Infrastructure Engineering (SCHIE) supports Microsoft’s global cloud infrastructure and online services. The AISIE team defines and delivers operational measures for hardware manufacturing, improving planning, quality, delivery, scale, and sustainability for Microsoft cloud hardware. The Physical Design Engineer II will contribute to physical design and signoff for semiconductor designs, helping deliver high-quality hardware infrastructure at scale, on time, and at low cost. The role requires working with limited direction, attention to detail, and clear communication of program progress, issues, and risks to management. Occasional travel may be required.

The position requires a relevant degree and technical engineering experience, or equivalent experience. The successful candidate must pass Microsoft’s Cloud Background Check upon hire or transfer and every two years thereafter. The role involves access to export-controlled information, so employment is conditional on verifying citizenship or another qualifying status and eligibility for access.

Requirements

• Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field and at least 1 year of technical engineering experience; or bachelor's degree in one of these fields and at least 2 years of technical engineering experience; or equivalent experience.
• Ability to meet Microsoft, customer, and/or government security screening requirements, including passing the Microsoft Cloud Background Check upon hire or transfer and every two years thereafter.
• Eligibility to access export-controlled information, with citizenship or other qualifying status verified using required documentation.
• Work independently with limited direction, pay close attention to detail, and communicate status, issues, and risks clearly.

Nice To Haves

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field and at least 6 years of technical engineering experience; or master's degree in one of these fields and at least 4 years; or doctorate in one of these fields and at least 2 years; or equivalent experience.
• At least 4 years of physical design experience, especially in synthesis, place and route (PNR), and signoff.
• At least 4 years of hands-on experience with EDA vendor tools such as RHSC, Star-RC, Fusion Compiler, VCLP, Primetime, Formality, Cadence Innovus, or Conformal.

Responsibilities

• Perform physical design tasks at block, sub-chip, and/or full-chip level, including design planning, synthesis, placement, clock tree synthesis, custom clocking, static timing analysis, physical verification, IR drop and EM checks, and formal equivalence checks.
• Deliver high-quality electromigration and IR drop signoff modeling methodology and drive overall EMIR convergence strategies.
• Analyze static timing analysis violations and drive their convergence.
• Develop best-in-class place-and-route strategies, particularly for blocks with challenging congestion and timing.
• Work with limited direction, maintain keen attention to detail, and provide management with clear updates on program progress, issues, and risks.
• Travel occasionally as required.

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level