Physical Design Engineer II

Microsoft • Washington, DC

4d • $102,100 - $219,200

About The Position

Microsoft’s Silicon, Cloud, Hardware, and Infrastructure Engineering organization develops infrastructure and foundational technologies for Microsoft’s online services and Azure. The AISIE team works on operational measures for hardware manufacturing, including planning, quality, delivery, scale, and sustainability. Microsoft is seeking a Physical Design Engineer II to help deliver cloud hardware infrastructure on time, at high volume, with high quality and low cost.

The engineer performs physical design work at the block, sub-chip, and/or full-chip level, including design planning, synthesis, placement, clock tree synthesis, custom clocking, static timing analysis, physical verification, IR drop and electromigration checks, and formal equivalence checks. The role drives EMIR sign-off methodology and convergence, resolves static timing violations, and develops place-and-route strategies for challenging blocks. The engineer is expected to work with limited direction, communicate progress and program risks clearly to management, and may occasionally travel.

Requirements

• Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field and at least 1 year of technical engineering experience; or bachelor’s degree in one of these fields and at least 2 years of technical engineering experience; or equivalent experience.
• Ability to meet Microsoft, customer, and/or government security screening requirements, including passing the Microsoft Cloud Background Check upon hire or transfer and every two years thereafter.
• Provide proof of citizenship, U.S. residency, or other protected status for export-control eligibility assessment; citizenship will be verified with a valid passport, with other applicable documents accepted for lawful permanent residents, refugees, and asylees.

Nice To Haves

• Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field and at least 6 years of technical engineering experience; or master’s degree in one of these fields and at least 4 years; or doctorate in one of these fields and at least 2 years; or equivalent experience.
• At least 4 years of experience in physical design, especially synthesis, place and route (PNR), and sign-off.
• At least 4 years of hands-on experience with EDA vendor tools such as RHSC, Star-RC, Fusion Compiler, VCLP, Primetime, Formality, Cadence Innovus, or Conformal.

Responsibilities

• Perform physical design tasks at block, sub-chip, and/or full-chip level, including design planning, synthesis, placement, clock tree synthesis, custom clocking, static timing analysis, physical verification, IR drop and electromigration checks, and formal equivalence checks.
• Deliver high-quality electromigration and IR drop sign-off modeling methodology and drive overall EMIR convergence strategies.
• Analyze and drive static timing analysis violations and their convergence.
• Deliver place-and-route strategies, particularly for blocks with challenging congestion and timing.
• Work with limited direction, pay close attention to detail, and provide management with clear status updates on progress, issues, and program risks.
• Travel occasionally as required.

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level