Memory Design Engineer

Intel Corporation•Austin, TX

4d•$105,650 - $200,340•Hybrid

About The Position

The Memory Design Engineer partners with domain experts across technology development, EDA vendors, and product design teams to develop high-quality memory technology collateral and enable innovations for next-generation high-performance, high-density, low-power embedded memory designs on Intel’s advanced CMOS process technologies. The role is part of Intel’s Advanced Design team within the Design Technology Platform organization, which focuses on pathfinding and development of advanced memory technology. The work supports memory collateral, IP, and product design across Intel process generations, helping internal and external customers bring products to market faster. The engineer defines and optimizes memory bitcells, array architectures, and peripheral circuits; leads memory pathfinding and power, performance, and area optimization through design-technology co-optimization and product design enablement; develops and validates memory libraries for PDK enablement; and designs and validates memory arrays, IP, innovative circuits, and test chips. The role is eligible for Intel’s hybrid work model, splitting time between an assigned Intel site and off-site work.

Requirements

Bachelor’s degree and 3 years of experience, or a master’s degree in Electrical Engineering, Computer Engineering, or a related STEM field and 2 or more years of experience, or a PhD with no experience.
Experience in customer circuit design, simulation, layout design, and verification.
Hands-on experience with relevant industry EDA tools and flows for digital and/or analog design and verification, such as Cadence Virtuoso, Synopsys StarRC, and Synopsys HSPICE.

Nice To Haves

Experience in memory bitcell and circuit design.
Experience with advanced CMOS process technologies and device physics.
Experience evaluating and balancing power, performance, and area trade-offs.
Experience designing, characterizing, and verifying custom memory circuits, such as SRAM, register files, and ROM.
Experience optimizing the physical design of custom circuits.

Responsibilities

Define, develop, and optimize advanced memory bitcells, array architectures, and peripheral circuits.
Lead memory pathfinding and optimize power, performance, and area through design-technology co-optimization and product design enablement.
Develop and validate memory libraries for PDK enablement across Intel’s advanced process technologies.
Design memory arrays and IP, develop innovative memory circuits, and execute and validate test chips.